lpc2300啟動(dòng)代碼分析

時(shí)間：2018-09-26 17:00:02

關(guān)鍵字：啟動(dòng)代碼 lpc2300

手機(jī)看文章

掃描二維碼
隨時(shí)隨地手機(jī)看文章

[導(dǎo)讀];/*****************************************************************************/;/* LPC2300.S: Startup file for Philips LPC2300 device series */;/******************************************************

;/*****************************************************************************/
;/* LPC2300.S: Startup file for Philips LPC2300 device series */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>> */
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools. */
;/* Copyright (c) 2007 Keil - An ARM Company. All rights reserved. */
;/* This software may only be used under the terms of a valid, current, */
;/* end user licence from KEIL for a compatible version of KEIL software */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/

;/*
; * The LPC2300.S code is executed after CPU Reset. This file may be
; * translated with the following SET symbols. In uVision these SET
; * symbols are entered under Options - ASM - Define.
; *
; * REMAP: when set the startup code initializes the register MEMMAP
; * which overwrites the settings of the CPU configuration pins. The
; * startup and interrupt vectors are remapped from:
; * 0x00000000 default setting (not remapped)
; * 0x40000000 when RAM_MODE is used
; *
; * RAM_MODE: when set the device is configured for code execution
; * from on-chip RAM starting at address 0x40000000.
; */
;/*
; 啟動(dòng)代碼是在CPU復(fù)位后執(zhí)行的
; 重映象：?jiǎn)?dòng)代碼初始化寄存器，設(shè)置好CPU的端腳，中斷向量
; 默認(rèn)的地址：0x00000000，不需要重新映象
; 當(dāng)程序在RAM中運(yùn)行時(shí)，地址位0x40000000
;
;
;*/

; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs

Mode_USR EQU 0x10 ;//定義用戶模式標(biāo)志代碼
Mode_FIQ EQU 0x11 ;//定義快速中斷模式標(biāo)志代碼
Mode_IRQ EQU 0x12 ;//定義普通中斷模式標(biāo)志代碼
Mode_SVC EQU 0x13 ;//定義管理模式標(biāo)志代碼
Mode_ABT EQU 0x17 ;//定義中止模式標(biāo)志代碼
Mode_UND EQU 0x1B ;//定義未定義模式標(biāo)志代碼
Mode_SYS EQU 0x1F ;//定義系統(tǒng)模式(特權(quán)模式)標(biāo)志代碼

I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled

;堆棧大小設(shè)置(字節(jié))
;// Stack Configuration (Stack Sizes in Bytes)
;// Undefined Mode <0x0-0xFFFFFFFF:8>
;// Supervisor Mode <0x0-0xFFFFFFFF:8>
;// Abort Mode <0x0-0xFFFFFFFF:8>
;// Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// Interrupt Mode <0x0-0xFFFFFFFF:8>
;// User/System Mode <0x0-0xFFFFFFFF:8>
;//

;定義各種模式堆棧的空間大小
UND_Stack_Size EQU 0x00000000 ;定義未定義模式堆棧大小
SVC_Stack_Size EQU 0x00000008 ;定義管理模式堆棧大小
ABT_Stack_Size EQU 0x00000000 ;定義中止模式堆棧大小
FIQ_Stack_Size EQU 0x00000000 ;定義快速中斷模式堆棧大小
IRQ_Stack_Size EQU 0x00000100 ;定義普通中斷模式堆棧大小
USR_Stack_Size EQU 0x00000400 ;定義用戶模式堆棧大小

; 將所有的堆棧大小進(jìn)行相加,得到總堆棧大小
ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size +
FIQ_Stack_Size + IRQ_Stack_Size)

;開辟一個(gè)名為STACK的段，定義為可寫可讀,字節(jié)對(duì)齊

AREA STACK, NOINIT, READWRITE, ALIGN=3

;定義堆棧的空間,用戶的在上面,ISR(中斷處理)的在下面

Stack_Mem SPACE USR_Stack_Size ;申請(qǐng)堆棧內(nèi)存空間

__initial_sp SPACE ISR_Stack_Size ;申請(qǐng)堆棧內(nèi)存空間

Stack_Top ;在這里放個(gè)標(biāo)號(hào),用來獲得堆棧頂部地址
;// Heap Configuration
;// Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;//

Heap_Size EQU 0x00000000 ;(Heap)堆是C語言動(dòng)態(tài)分配內(nèi)存使用,是編譯器自己設(shè)定,如果沒

;有Printf ,New,Malloc之類的函數(shù)可以不設(shè)置

;開辟一個(gè)名為HEAP的段，定義為可寫可讀，字節(jié)對(duì)齊

AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base ;指定堆的開頭
Heap_Mem SPACE Heap_Size
__heap_limit ;指定堆的結(jié)尾

; System Control Block (SCB) Module Definitions
SCB_BASE EQU 0xE01FC000 ; SCB Base Address
PLLCON_OFS EQU 0x80 ; PLL Control Offset
PLLCFG_OFS EQU 0x84 ; PLL Configuration Offset
PLLSTAT_OFS EQU 0x88 ; PLL Status Offset
PLLFEED_OFS EQU 0x8C ; PLL Feed Offset
CCLKCFG_OFS EQU 0x104 ; CPU Clock Divider Reg Offset
USBCLKCFG_OFS EQU 0x108 ; USB Clock Divider Reg Offset
CLKSRCSEL_OFS EQU 0x10C ; Clock Source Select Reg Offset
SCS_OFS EQU 0x1A0 ; System Control and Status Reg Offset
PCLKSEL0_OFS EQU 0x1A8 ; Peripheral Clock Select Reg 0 Offset
PCLKSEL1_OFS EQU 0x1AC ; Peripheral Clock Select Reg 1 Offset

; Constants
OSCRANGE EQU (1<<4) ; Oscillator Range Select
OSCEN EQU (1<<5) ; Main oscillator Enable
OSCSTAT EQU (1<<6) ; Main Oscillator Status
PLLCON_PLLE EQU (1<<0) ; PLL Enable
PLLCON_PLLC EQU (1<<1) ; PLL Connect
PLLSTAT_M EQU (0x7FFF<<0) ; PLL M Value
PLLSTAT_N EQU (0xFF<<16) ; PLL N Value
PLLSTAT_PLOCK EQU (1<<26) ; PLL Lock Status

;時(shí)鐘的建立
;// Clock Setup
;// System Controls and Status Register (SCS) ;系統(tǒng)控制和狀態(tài)寄存器
;// OSCRANGE: Main Oscillator Range Select ;主晶振的范圍選擇
;// <0=> 1 MHz to 20 MHz
;// <1=> 15 MHz to 24 MHz
;// OSCEN: Main Oscillator Enable ;主晶振使能
;//
;//

;時(shí)鐘源選擇
;//
;// Clock Source Select Register (CLKSRCSEL) ;PLL時(shí)鐘源選擇
;// CLKSRC: PLL Clock Source Selection
;// <0=> Internal RC oscillator ;內(nèi)部RC
;// <1=> Main oscillator;主晶振
;// <1=> RTC oscillator ;實(shí)時(shí)時(shí)鐘晶振
;//

;PLL的配置
;//
;// PLL Configuration Register (PLLCFG)
;// PLL_clk = (2* M * PLL_clk_src) / N
;// MSEL: PLL Multiplier Selection;PLL倍頻
;// <1-32768><#-1>
;// M Value
;// NSEL: PLL Divider Selection ;PLL分頻
;// <1-256><#-1>
;// N Value
;//

;CPU時(shí)鐘配置
;//
;// CPU Clock Configuration Register (CCLKCFG)
;// CCLKSEL: Divide Value for CPU Clock from PLL ;系統(tǒng)的頻率,由PLL分頻得到
;// <1-256><#-1>
;//

;USB時(shí)鐘配置
;//
;// USB Clock Configuration Register (USBCLKCFG)
;// USBSEL: Divide Value for USB Clock from PLL ;USB的頻率,由PLL分頻得到
;// <1-16><#-1>
;//

;外設(shè)時(shí)鐘選擇
;//
;// Peripheral Clock Selection Register 0 (PCLKSEL0)
;// PCLK_WDT: Peripheral Clock Selection for WDT ;WDT的外設(shè)時(shí)鐘
;// <0=> Pclk = Cclk / 4 ;系統(tǒng)時(shí)鐘/4
;// <1=> Pclk = Cclk ;系統(tǒng)時(shí)鐘
;// <2=> Pclk = Cclk / 2 ;系統(tǒng)時(shí)鐘/2
;// <3=> Pclk = Hclk / 8 ;AHB總線時(shí)鐘/2

;// PCLK_TIMER0: Peripheral Clock Selection for TIMER0 ;TIMER0時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_TIMER1: Peripheral Clock Selection for TIMER1 ;TIMER0時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_UART0: Peripheral Clock Selection for UART0 ;UART0時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_UART1: Peripheral Clock Selection for UART1 ;UART1時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_PWM0: Peripheral Clock Selection for PWM0 ;PWM0時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_PWM1: Peripheral Clock Selection for PWM1 ;PWM1時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_I2C0: Peripheral Clock Selection for I2C0 ;I2C0時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_SPI: Peripheral Clock Selection for SPI ;SPI時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_RTC: Peripheral Clock Selection for RTC ;RTC 時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_SSP1: Peripheral Clock Selection for SSP1 ;SSP1時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_DAC: Peripheral Clock Selection for DAC ;DAC時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_ADC: Peripheral Clock Selection for ADC ;ADC時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_CAN1: Peripheral Clock Selection for CAN1;CAN總線1時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 6
;// PCLK_CAN2: Peripheral Clock Selection for CAN2 ;CAN總線2時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 6
;// PCLK_ACF: Peripheral Clock Selection for ACF ;高級(jí)通訊時(shí)鐘選擇
;// <0=> Pclk = Cclk / 4 ;在這為以太網(wǎng)
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 6
;//

;外設(shè)時(shí)鐘選擇
;//
;// Peripheral Clock Selection Register 1 (PCLKSEL1)
;// PCLK_BAT_RAM: Peripheral Clock Selection for the Battery Supported RAM ;電池RAM
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_GPIO: Peripheral Clock Selection for GPIOs ;GPIO 時(shí)鐘
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_PCB: Peripheral Clock Selection for Pin Connect Block ;引腳連接模塊時(shí)鐘
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_I2C1: Peripheral Clock Selection for I2C1 ;I2C1時(shí)鐘
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8 ;SSP1時(shí)鐘
;// PCLK_SSP0: Peripheral Clock Selection for SSP0
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_TIMER2: Peripheral Clock Selection for TIMER2;TIMER2時(shí)鐘
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_TIMER3: Peripheral Clock Selection for TIMER3 ;TIMER3時(shí)鐘
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_UART2: Peripheral Clock Selection for UART2;UART2時(shí)鐘
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_UART3: Peripheral Clock Selection for UART3 ;UART3時(shí)鐘
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8;I2C2時(shí)鐘
;// PCLK_I2C2: Peripheral Clock Selection for I2C2
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_I2S: Peripheral Clock Selection for I2S ;I2S(數(shù)字音頻設(shè)備)時(shí)鐘
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_MCI: Peripheral Clock Selection for MCI ;MCI(媒體控制接口)時(shí)鐘
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;// PCLK_SYSCON: Peripheral Clock Selection for System Control Block;系統(tǒng)控制模塊時(shí)鐘
;// <0=> Pclk = Cclk / 4
;// <1=> Pclk = Cclk
;// <2=> Pclk = Cclk / 2
;// <3=> Pclk = Hclk / 8
;//
;//
CLOCK_SETUP EQU 1
SCS_Val EQU 0x00000020 ;使用外部晶振
CLKSRCSEL_Val EQU 0x00000001 ;選擇主晶振的PLL輸出
;Fcco(電流控制振蕩器)的范圍為275MHZ~550MHZ
;Fin 的范圍為32k~50MHZ
;Fcco=(2*M*Fin)/N
;M，N在寫入寄存器的時(shí)候減1

;Fcco=(2*12*12M)/1=288M,LPC2378的FCCO范圍:275MHZ~550MHZ
PLLCFG_Val EQU 0x0000000B

;Fcclk=PLL/CCLKSEL=288M/4=72MHZ
CCLKCFG_Val EQU 0x00000003 ;CCLKCFG的值必須為0或者奇數(shù),否則會(huì)引起器件的不正確操作

;USB時(shí)鐘=PLL/USBSEL=288/6=48MHZ
USBCLKCFG_Val EQU 0x00000005

;外設(shè)時(shí)鐘=CCLK/4=72MHZ/4=18MHZ
PCLKSEL0_Val EQU 0x00000000
PCLKSEL1_Val EQU 0x00000000

;內(nèi)存加速模塊
; Memory Accelerator Module (MAM) definitions
MAM_BASE EQU 0xE01FC000 ; MAM Base Address
MAMCR_OFS EQU 0x00 ; MAM Control Offset
MAMTIM_OFS EQU 0x04 ; MAM Timing Offset

;內(nèi)存加速模塊控制
;// MAM Setup
;// MAM Control
;// <0=> Disabled ;全部禁止
;// <1=> Partially Enabled ;部分使能
;// <2=> Fully Enabled ;全部使能
;// Mode ;保留
;// MAM Timing
;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
;// <4=> 4 <5=> 5 <6=> 6 <7=> 7
;// Fetch Cycles
;//
MAM_SETUP EQU 1 ; MAM 設(shè)置程序判斷標(biāo)志
MAMCR_Val EQU 0x00000002 ; MAM全部使能
MAMTIM_Val EQU 0x00000004 ; MAM，4個(gè)CPU時(shí)鐘訪問一次內(nèi)存

; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.

;程序入口點(diǎn),每個(gè)ARM必須至少要有一個(gè)入口

AREA RESET, CODE, READONLY
ARM

; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.

;配置各中斷向量
Vectors LDR PC, Reset_Addr ;//引入復(fù)位地址
LDR PC, Undef_Addr ;//引入未定義地址
LDR PC, SWI_Addr ;//引入軟件中斷地址
LDR PC, PAbt_Addr ;//引入中止(預(yù)取指)地址
LDR PC, DAbt_Addr ;//引入中止(數(shù)據(jù))地址

NOP ; Reserved Vector

LDR PC, IRQ_Addr ;//引入中斷地址
LDR PC, [PC, #-0x0120] ;Vector from VicVectAddr
LDR PC, FIQ_Addr ;//引入快速中斷地址

Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SWI_Addr DCD SWI_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler

Undef_Handler B Undef_Handler;B為跳轉(zhuǎn)指令,跳轉(zhuǎn)到某個(gè)地方
SWI_Handler B SWI_Handler
PAbt_Handler B PAbt_Handler
DAbt_Handler B DAbt_Handler
IRQ_Handler B IRQ_Handler
FIQ_Handler B FIQ_Handler

; Reset Handler

EXPORT Reset_Handler ;導(dǎo)出定義一個(gè)全局函數(shù)名變量
Reset_Handler

;設(shè)置時(shí)鐘
; Setup Clock
IF CLOCK_SETUP != 0
LDR R0, =SCB_BASE
;使PLL配置寄存器有效
MOV R1, #0xAA
MOV R2, #0x55
;配置使能PLL
; Configure and Enable PLL
LDR R3, =SCS_Val ; Enable main oscillator
STR R3, [R0, #SCS_OFS] ;SCS<=SCS_Val ，主晶振使能，使用外部引腳的晶振

IF (SCS_Val:AND:OSCEN) != 0 ;晶振是否已經(jīng)穩(wěn)定，繼續(xù)判斷
OSC_Loop LDR R3, [R0, #SCS_OFS] ; Wait for main osc stabiliz 等待主晶振穩(wěn)定
ANDS R3, R3, #OSCSTAT
BEQ OSC_Loop ;
ENDIF

LDR R3, =CLKSRCSEL_Val ; Select PLL source clock
STR R3, [R0, #CLKSRCSEL_OFS] ; CLKSRCSEL<=0x00000001 ,選擇主晶振作為PLL時(shí)鐘源

LDR R3, =PLLCFG_Val; PLLCFG <=0x0000000B，M，N賦值
STR R3, [R0, #PLLCFG_OFS]

STR R1, [R0, #PLLFEED_OFS]; PLLFEED <=0xAA
STR R2, [R0, #PLLFEED_OFS]; PLLFEED <=0x55

MOV R3, #PLLCON_PLLE; PLLCON <= 1<<0，PLL使能
STR R3, [R0, #PLLCON_OFS]

STR R1, [R0, #PLLFEED_OFS]; PLLFEED <=0xAA
STR R2, [R0, #PLLFEED_OFS]; PLLFEED <=0x55

;等待PLL鎖存
; Wait until PLL Locked
PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]；;讀PLLSTAT
ANDS R3, R3, #PLLSTAT_PLOCK ;是否PLL已經(jīng)鎖定
BEQ PLL_Loop

M_N_Lock LDR R3, [R0, #PLLSTAT_OFS] ;讀PLLSTAT的狀態(tài)
LDR R4, =(PLLSTAT_M:OR:PLLSTAT_N) ;讀M，N的值
AND R3, R3, R4 ;R3=R3&&R4，M，N和鎖存狀態(tài)

LDR R4, =PLLCFG_Val ;R4<=M,N的值
EORS R3, R3, R4 ;M，N的設(shè)定值是否與讀出值相等
BNE M_N_Lock

;設(shè)置CPU時(shí)鐘
; Setup CPU clock divider
MOV R3, #CCLKCFG_Val;CPU時(shí)鐘為PLL時(shí)鐘/5
STR R3, [R0, #CCLKCFG_OFS]

;設(shè)置USB時(shí)鐘
; Setup USB clock divider
LDR R3, =USBCLKCFG_Val ;USB時(shí)鐘為PLL時(shí)鐘/6
STR R3, [R0, #USBCLKCFG_OFS]

;設(shè)置外設(shè)時(shí)鐘
; Setup Peripheral Clock
LDR R3, =PCLKSEL0_Val ;外設(shè)時(shí)鐘=CPU時(shí)鐘/4=57.6MHZ/4=14.4MHZ
STR R3, [R0, #PCLKSEL0_OFS]
LDR R3, =PCLKSEL1_Val
STR R3, [R0, #PCLKSEL1_OFS]

;開啟PLL時(shí)鐘
; Switch to PLL Clock
MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) ;PLL使能并連接
STR R3, [R0, #PLLCON_OFS]

STR R1, [R0, #PLLFEED_OFS] ;PLLFEED <=0xAA
STR R2, [R0, #PLLFEED_OFS] ;PLLFEED <=0x55
ENDIF ; CLOCK_SETUP

;設(shè)置MAM 存儲(chǔ)器加速模塊
; Setup MAM
IF MAM_SETUP != 0
LDR R0, =MAM_BASE
MOV R1, #MAMTIM_Val ;4個(gè)CPU時(shí)鐘訪問依次內(nèi)存
STR R1, [R0, #MAMTIM_OFS]

MOV R1, #MAMCR_Val ;內(nèi)存加速全部使能
STR R1, [R0, #MAMCR_OFS]
ENDIF ; MAM_SETUP

;內(nèi)存映射（當(dāng)中斷向量是在內(nèi)存）
; Memory Mapping (when Interrupt Vectors are in RAM)
MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
IF :DEF:REMAP
LDR R0, =MEMMAP
IF :DEF:RAM_MODE
MOV R1, #2
ELSE
MOV R1, #1
ENDIF
STR R1, [R0]
ENDIF

; 初始化中斷堆棧系統(tǒng)
; Initialise Interrupt System
; ...

;設(shè)置每一個(gè)工作模式堆棧
; Setup Stack for each mode

LDR R0, =Stack_Top ;R0設(shè)置為堆棧的首地址

; 進(jìn)入未定義模式，并設(shè)置堆棧指針
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size ;每設(shè)置完一種模式的堆棧,就減去,得到下一堆棧的首地址

;進(jìn)入中止模式，并設(shè)置堆棧指針
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size

;進(jìn)入快速中斷模式，并設(shè)置堆棧指針
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size

;進(jìn)入普通中斷模式，并設(shè)置堆棧指針
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size

;進(jìn)入管理(特權(quán))模式，并設(shè)置堆棧指針
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size

; 進(jìn)入用戶模式，并設(shè)置堆棧指針
; Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
IF :DEF:__MICROLIB

EXPORT __initial_sp

ELSE

MOV SP, R0
SUB SL, SP, #USR_Stack_Size

ENDIF

;進(jìn)入C代碼, __main前的下劃線不要去,進(jìn)入C代碼庫(kù)的初始化函數(shù),再進(jìn)入用戶的函數(shù)
; Enter the C code

IMPORT __main
LDR R0, =__main
BX R0

IF :DEF:__MICROLIB

EXPORT __heap_base
EXPORT __heap_limit

ELSE

;用戶設(shè)置堆棧程序(C外部接口:用于動(dòng)態(tài)申請(qǐng)內(nèi)存使用)
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY

IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap