什么是競(jìng)爭(zhēng)冒險(xiǎn)?如何避免?
時(shí)間:2021-11-11 14:49:26
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[導(dǎo)讀]競(jìng)爭(zhēng)冒險(xiǎn)這個(gè)含義其實(shí)廣泛存在各個(gè)領(lǐng)域,本質(zhì)上是指當(dāng)兩個(gè)或多個(gè)進(jìn)程同時(shí)訪問(wèn)一個(gè)相同對(duì)象的場(chǎng)景。組合邏輯環(huán)moduleCMBLOP(o,a,b,c);outputo;inputa,b,c;rego;wirem=a|o;wiren=b|m;always@(corn)o=c|n;endm...
競(jìng)爭(zhēng)冒險(xiǎn)這個(gè)含義其實(shí)廣泛存在各個(gè)領(lǐng)域,本質(zhì)上是指當(dāng)兩個(gè)或多個(gè)進(jìn)程同時(shí)訪問(wèn)一個(gè)相同對(duì)象的場(chǎng)景。
組合邏輯環(huán)
Verilog語(yǔ)句塊有很多是并發(fā)的,不同的仿真器執(zhí)行的順序可能不一致?Write - Write Contention Race
組合邏輯環(huán)
module CMBLOP (o, a, b, c);
output o;
input a, b, c;
reg o;
wire m = a | o;
wire n = b | m;
always @(c or n)
o = c | n;
endmodule
在一般的數(shù)字設(shè)計(jì)中不用使用組合邏輯環(huán),需要在其中進(jìn)行插拍(異步設(shè)計(jì)除外)。?仿真競(jìng)爭(zhēng)冒險(xiǎn):在兩個(gè)或兩個(gè)以上變量之間沒(méi)有電路邏輯環(huán),但有一個(gè)仿真反饋路徑。module SIMLOP;
wire a, c;
reg b;
always @ (a or c) begin
b = a;
end
assign c = b;
endmodule
Verilog語(yǔ)句塊有很多是并發(fā)的,不同的仿真器執(zhí)行的順序可能不一致?Write - Write Contention Race
module wr_wr_race (clk, a, b); //Write – Write Race
input clk,b;
output a;
wire d1, d2;
reg c1, c2, a;
always @(posedge clk) c1 = b;
always @(posedge clk) c2 = ~b;
assign d1 = c1;
assign d2 = c2;
always @(d1) a = d1;
always @(d2) a = d2;
endmodule
Write-Write競(jìng)爭(zhēng)冒險(xiǎn)可以通過(guò)將寫入操作合并成單個(gè)進(jìn)程來(lái)解決。?Read - Write Contention Racealways @(posedge clk) /* write process */
status_reg = new_val;
always @(posedge clk) /* read process */
status_output = status_reg;
上述讀寫競(jìng)爭(zhēng)冒險(xiǎn)可以通過(guò)non-blocking賦值解決。?避免競(jìng)爭(zhēng)冒險(xiǎn)的幾個(gè)建議:1.使用non blocking賦值。2.一個(gè)寄存器只在單個(gè)語(yǔ)句塊中賦值。3.assign賦值語(yǔ)句僅用來(lái)連接,不用來(lái)產(chǎn)生邏輯。