基于網(wǎng)絡(luò)編碼的多信源組播通信系統(tǒng)，包括源代碼，原理圖等 (三)

ctrl bus(8位)

Data bus（64位）

ff

module header

00

Pkt data1

00

……

xy(xy≠00)

Last pkt data

Signal name

Bit width

Input or output

description

Input_fifo_data_1

64

input

Input data bus from “input FIFO 1”

Input_fifo_ctrl_1

8

input

Input ctrl bus from “input FIFO 1”

Input_fifo_empty_1

1

input

1=input FIFO is empty,0=otherwise

Input_fifo_rd_en_1

1

output

Read enable

Input_fifo_data_2

64

input

Input data bus from “input FIFO 2”

Input_fifo_ctrl_2

8

input

Input ctrl bus from “input FIFO 2”

Input_fifo_empty_2

1

input

1=input FIFO is empty,0=otherwise

Input_fifo_rd_en_2

1

output

Read enable

Data_arbiter_ctrl_1

64

output

Output data bus to “control module”

Ctrl_arbiter_ctrl_1

8

Output

Output ctrl bus to “control module”

Val_arbitrer_ctrl_1

1

Output

1=data from input arbiter 1 to head splitter 1 is valid, 0=otherwise

Rdy_arbiter_ctrl_1

1

Input

1=module “head splitter 1” is ready to receive

Data_arbiter_ctrl_2

64

output

Output data bus to “control module”

Ctrl_arbiter_ctrl_2

8

Output

Output ctrl bus to “control module”

Val_arbitrer_ctrl_2

1

Output

1=data from input arbiter 2 to head splitter 2 is valid, 0=otherwise

Rdy_arbiter_ctrl_2

1

Input

1=module “head splitter 2” is ready to receive, 0=otherwise

Data_arbiter_out_1

64

output

Output data bus to “output arbiter module”

Ctrl_arbiter_out_1

8

Output

Output ctrl bus to “output arbiter module”

Val_arbiter_out_1

1

Output

1=data from input arbiter 1 to output arbiter is valid, 0=otherwise

Rdy_arbiter_out_1

1

Input

1=module “output arbiter” is ready to receive from input arbiter 1, 0=otherwise

Data_arbiter_out_2

64

output

Output data bus to “output arbiter module”

Ctrl_arbiter_out_2

8

Output

Output ctrl bus to “output arbiter module”

Val_arbiter_out_2

1

Output

1=data from input arbiter 2 to output arbiter is valid, 0=otherwise

Rdy_arbiter_out_2

1

Input

1=module “output arbiter” is ready to receive from input arbiter 2, 0=otherwise

clk

1

Input

System clock, running at 125MHz

Rst_n

1

input

System asynchronous reset signal

Sub module name

quantity

description

Head_spliter

2

Split head and payload, send head to “head info extractor”, send payload to “FIFO ctrl payload”

Head_info_extractor

2

Receive head from “head splitter”, extract “source number”, generate “generation number”. Store legacy head and packing info head respectively in “FIFO ctrl legacy” and “FIFO ctrl packinginfo”

Control_arbiter

1

Detect ctrl bus to determine whether should process both channels synchronously or hold one channel and process the other.

FIFO ctrl payload

2

Standard FIFO generated by CoreGen, store payload

FIFO ctrl legacy

2

Standard FIFO generated by CoreGen, store legacy head

FIFO ctrl packinginfo

2

Standard FIFO generated by CoreGen, store packing info head

Signal name

Bit width

Input or output

description

Data_arbiter_ctrl_1

64

Input

Input data bus from “input arbiter 1”

Ctrl_arbiter_ctrl_1

8

Input

Input ctrl bus from “input arbiter 1”

Val_arbiter_ctrl_1

1

Input

1=data from input arbiter 1 to head splitter 1 is valid, 0=otherwise

Rdy_arbiter_ctrl_1

1

output

1=module “head splitter 1” is ready to receive from input arbiter 1, 0=otherwise

Data_arbiter_ctrl_2

64

Input

Input data bus from “input arbiter 2”

Ctrl_arbiter_ctrl_2

8

Input

Input ctrl bus from “input arbiter 2”

Val_arbiter_ctrl_2

1

Input

1=data from input arbiter 2 to head splitter 2 is valid, 0=otherwise

Rdy_arbiter_ctrl_2

1

output

1=module “head splitter 2” is ready to receive from input arbiter 2, 0=otherwise

Data_payloadfifo_router_1

64

output

output data bus to “payload router”

Ctrl_payloadfifo_router_1

8

output

Output ctrl bus to “payload router”

Rd_en_payloadfifo_router_1

1

Input

Read enable

Empty_payloadfifo_router_1

1

output

1=FIFO ctil payload 1 is empty,0=otherwise

Data_payloadfifo_router_2

64

output

output data bus to “payload router”

Ctrl_payloadfifo_router_2

8

output

Output ctrl bus to “payload router”

Rd_en_payloadfifo_router_2

1

Input

Read enable

Empty_payloadfifo_router_2

1

output

1=FIFO ctrl payload 2 is empty,0=otherwise

Data_center_legacyfifo_1

64

Output

Output data bus to “packing center”

Rd_en_center_legacyfifo_1

1

Input

Read enable

Data_center_packingfifo_1

14

Output

Output data bus to “packing center”

Rd_en_center_packingfifo_1

1

input

Read enable

Data_center_legacyfifo_2

64

Output

Output data bus to “packing center”

Rd_en_center_legacyfifo_2

1

Input

Read enable

Data_center_packingfifo_2

14

Output

Output data bus to “packing center”

Rd_en_center_packingfifo_2

1

input

Read enable

clk

1

input

System clock, running at 125MHz

Rst_n

1

input

System asynchronous reset signal

Submodule name

quantity

description

Payload router

1

Determine by the arrival of packets from both channels, whether should process coding or transport directly to packing module

M64×8 multiplier

2

Multiply 64-bit data from “payload router” by 8-bit random number from “prng tap16”

Prng tap16

1

8-bit random number generator

M72×72 adder

1

72-bit by 72-bit full adder

M72to64 converter

1

Convert data bus width from 72-bit to 64-bit

Signal name  

Bit width

I/O

description

Data_payloadfifo_router_1

64

Input

Input data bus from “FIFO ctrl payload 1”

Ctrl_payloadfifo_router_1

8

Input

Input ctrl bus from “FIFO ctrl payload 1”

empty_payloadfifo_router_1

1

Input

1=FIFO ctrl payload 1 is empty,0=otherwise

Rd_en_payloadfifo_rouer_1

1

output

Read enable

Data_payloadfifo_router_2

64

Input

Input data bus from “FIFO ctrl payload 2”

Ctrl_payloadfifo_router_2

8

Input

Input ctrl bus from “FIFO ctrl payload 2”

empty_payloadfifo_router_2

1

Input

1=FIFO ctrl payload 2 is empty,0=otherwise

Rd_en_payloadfifo_rouer_2

1

output

Read enable

Router status

3

output

Output FSM state signal to “packing FIFO” and “packing center”, coordinate with the control of packing procedure

Data_router_packingfifo

73

output

Output data bus to “packing FIFO”. Bit 64 is set to “0” to indicate this is an uncoded packet

Wr_en_router_packingfifo

1

output

Write enable

Rdy_router_packingfifo

1

input

1=module “packing FIFO” is ready to receive from payload router, 0=otherwise

Empty_packingfifo

1

input

1=FIFO packing is empty,0=otherwise

Data_converter_packingfifo

73

output

Output data bus to “packing FIFO”. Bit 64 is set to “1” to indicate this is a coded packet

Wr_en_converter_packingfifo

1

Output

Write enable

Rdy_converter_packingfifo

1

output

1=module “packing FIFO” is ready to receive from m72to64 converter, 0=otherwise

Empty_converterfifo

1

output

1=FIFO converter is empty,0=otherwise

Rand_num_1

8

output

Output random number 1 to “packing center”

Rand_num_2

8

output

Output random number 2 to “packing center”

clk

1

input

System clock running at 125MHz

Rst_n

1

input

System asynchronous reset signal

Sub module name 

quantity

Description

Packing FIFO

1

Receive and store processed packets before being packed in “packing center”

Packing center

1

Packing payload with all sorts of heads

Signal name

Bit width

I/O

Description

Data_router_packingfifo

73

input

Input data bus from “payload router”. Bit 64 is set to “0” to indicate this is an uncoded packet

Wr_en_router_packingfifo

1

Input

Write enable

Rdy_router_packingfifo

1

Output

1=module “packing FIFO” is ready to receive from payload router, 0=otherwise

Router_status

3

input

Input FSM state signal to coordinate with the control of  “packing FIFO”

Empty_packingfifo

1

output

1=FIFO packing is empty,0=otherwise

Data_converter_packingfifo

73

input

Input data bus from “m72to64 converter”. Bit 64 is set to “1” to indicate this is a coded packet

Wr_en_converter_packingfifo

1

Input

Write enable

Rdy_converter_packingfifo

1

Output

1=module “packing FIFO” is ready to receive from m72to64 converter, 0=otherwise

Empty_converterfifo

1

Input

1=FIFO converter is empty,0=otherwise

Data_center_legacyfifo_1

64

Input

Input data bus from “FIFO ctrl legacy 1”

Rd_en_center_legacyfifo_1

1

output

Read enable

Data_center_packinginfo_1

14

Input

Input data bus from “FIFO ctrl packinginfo 1”

Rd_en_center_packinginfo_1

1

output

Read enable

Data_center_legacyfifo_2

64

Input

Input data bus from “FIFO ctrl legacy 2”

Rd_en_center_legacyfifo_2

1

output

Read enable

Data_center_packinginfo_2

14

Input

Input data bus from “FIFO ctrl packinginfo 2”

Rd_en_center_packinginfo_2

1

output

Read enable

Rand_num_center_1

8

input

Input random number from “m64×64 multiplier 1”

Rand_num_center_2

8

input

Input random number from “m64×64 multiplier 2”

Out_data_out_0

64

output

Output data bus to “output arbiter”

Out_ctrl_out_0

8

Output

Output ctrl bus to “output arbiter”

Data_val_out_0

1

Output

1=data from packing center to output arbiter is valid, 0=otherwise

Rdy_out_0

1

Input

1=output arbiter is ready to receive from packing center, 0=otherwise

clk

1

Input

System clock running at 125 MHz

Rst_n

1

input

System asynchronous reset signal

Signal name

Bit width

Input or output

Description

Out_data_out_0

64

input

input data bus from “packing center”

Out_ctrl_out_0

8

Input

input ctrl bus from “packing center”

Data_val_out_0

1

Input

1=data from packing center to output arbiter is valid, 0=otherwise

Rdy_out_0

1

output

1=output arbiter is ready to receive from packing center, 0=otherwise

Out_data_out_1

64

input

input data bus from “input arbiter 1”

Out_ctrl_out_1

8

Input

input ctrl bus from “input arbiter 1”

Data_val_out_1

1

Input

1=data from input arbiter 1 to output arbiter is valid, 0=otherwise

Rdy_out_1

1

output

1=output arbiter is ready to receive from input arbiter 1, 0=otherwise

Out_data_out_2

64

input

input data bus from “input arbiter 2”

Out_ctrl_out_2

8

Input

input ctrl bus from “input arbiter 2”

Data_val_out_2

1

Input

1=data from input arbiter 2 to output arbiter is valid, 0=otherwise

Rdy_out_2

1

output

1=output arbiter is ready to receive from input arbiter 2, 0=otherwise

Out_data_mac

64

output

output data bus to “MAC Layer”

Out_ctrl_mac

8

Output

output ctrl bus to “MAC Layer”

Data_val_mac

1

Output

1=data from output arbiter to MAC layer is valid, 0=otherwise

Rdy_mac

1

Input

1=MAC layer is ready to receive from output arbiter, 0=otherwise

clk

1

Input

System clock running at 125MHz

Rst_n

1

input

System asynchronous reset signal

信號名稱

位寬 bits

I/O

描述

in_data_n(n:0、1、2、3)

64

input

從MAC層輸入的data數(shù)據(jù)

in_ctrl_n(n:0、1、2、3)

8

input

從MAC層輸入的ctrlbus數(shù)據(jù)

in_wr_n(n:0、1、2、3)

1

input

從MAC層輸入的數(shù)據(jù)寫使能信號（1為有效）

in_rdy_n(n:0、1、2、3)

1

output

輸出至MAC層的準(zhǔn)備信號（1為準(zhǔn)備完畢，可以寫入）

out_data

64

output

輸出至forward模塊的data數(shù)據(jù)

out_ctrl

8

output

輸出至froward模塊的ctrl數(shù)據(jù)

out_wr

1

output

輸出至forward模塊的寫使能信號（1為寫使能有效）

out_rdy

1

input

從forward模塊輸入的準(zhǔn)備信號（1為準(zhǔn)備好，可以寫入）

信號名稱

位寬 bits

I/O

描述

out_data

64

input

從input_arbiter模塊輸出的data數(shù)據(jù)

out_ctrl

8

input

從input_arbiter模塊輸出的ctrl數(shù)據(jù)

out_wr

1

input

從input_arbiter模塊輸出的寫使能信號（1為寫使能有效）

out_rdy

1

input

輸出至input_arbiter模塊的準(zhǔn)備使能信號（1為準(zhǔn)備使能有效）

out_data_n(n:0、1、2、3)

64

output

輸出至MAC層的data數(shù)據(jù)

out_ctrl_n(n:0、1、2、3)

8

output

輸出至MAC層的ctrlbus數(shù)據(jù)

out_wr_n(n:0、1、2、3)

1

output

輸出至MAC層的數(shù)據(jù)寫使能信號（1為有效）

out_rdy_n(n:0、1、2、3)

1

intput

從MAC層輸入的準(zhǔn)備信號（1為準(zhǔn)備完畢，可以寫入）

信號名稱

位寬 bit

I/O

描述

Wr_vld_arb

1

寫DRAM控制器有效

Out_data_0

64

輸出至DRAM的data

Out_ctrl_0

8

輸出至DRAM德ctrl

Src_gen_seq

24

信源號、代的編號

Cam_vld

1

寫CAM控制器有效

Port_num_dram

2

數(shù)據(jù)的接收端口號

Out_data_1

64

輸出至output arbiter的data

Out_ctrl_1

8

輸出至output arbiter的ctrl

Wr_vld_1

1

輸出至output arbiter信號有效

信號名稱

位寬bits

I/O

描述

out_data_3

64

O

輸出至MAC層的數(shù)據(jù)總線

out_ctrl_3

8

O

輸出至MAC層的控制總線

out_wr_3

1

O

輸出有效

out_rdy_3

1

I

MAC層空閑標(biāo)志

dcod_data_0

64

I

已經(jīng)解碼的IP數(shù)據(jù)包的數(shù)據(jù)總線

dcod_ctrl_0

8

I

已經(jīng)解碼的IP數(shù)據(jù)包的控制總線

wr_vld_0

1

I

寫有效

wr_rdy_0

1

O

接收數(shù)據(jù)空閑標(biāo)志

non_ip_data

64

I

非IP數(shù)據(jù)包數(shù)據(jù)總線

non_ip_ctrl

8

I

非IP數(shù)據(jù)包控制總線

wr_vld_1

1

I

寫有效

wr_rdy_1

1

O

接收數(shù)據(jù)空閑標(biāo)志

信號名稱

位寬bits

I/O

描述

rd_dcod_reg_req_0

1

I

讀取解碼標(biāo)志位請求

rd_dcod_src_gen_0

12

I

要讀取的數(shù)據(jù)包的信源號和代編號

req_ack_vld_0

1

O

輸出有效

alredy_decod_0

1

O

解碼標(biāo)志（“1”代表已經(jīng)解碼，“0”代表未解碼）

rd_dcod_reg_req_1

1

I

讀取解碼標(biāo)志位請求

rd_dcod_src_gen_1

12

I

要讀取的數(shù)據(jù)包的信源號和代編號

req_ack_vld_1

1

O

輸出有效

alredy_decod_1

1

O

解碼標(biāo)志（為1時(shí)代表已經(jīng)解碼，為0時(shí)未解碼）

set_req

1

I

置位請求

set_src_gen

12

I

需要置位的數(shù)據(jù)包（表示已經(jīng)解碼完畢）

set_info_vld

1

I

置位信息有效

set_ack

1

O

置位請求響應(yīng)

reset_req

1

I

復(fù)位請求

reset_src_gen

12

I

需要復(fù)位的數(shù)據(jù)包（表示解碼后已發(fā)送完畢）

reset_info_vld

1

I

復(fù)位信息有效

reset_ack

1

O

復(fù)位請求響應(yīng)

Signal Group

Signal Name

Direction

Bits

Description

Request Negotiation

p_wr_req

from user logic to block-of-data rd/wr module

1

1=request for write transfer (data are from user logic to DRAM), 0=otherwise

Request Negotiation

p_wr_ptr

from user logic to block-of-data rd/wr module

PKT_MEM_PTR_WIDTH

the start address of DRAM for transfer. Each unit is 16-byte piece

Request Negotiation

p_wr_ack

from block-of-data rd/wr module to user logic

1

1=the arbiter acknowledges that the write requester can proceed, 0=otherwise

Data Transfer

p_wr_data_vld

from user logic to block-of-data rd/wr module

1

1=the write data is valid, 0=otherwise

Data Transfer

p_wr_data

from user logic to block-of-data rd/wr module

PKT_DATA_WIDTH

the data transferred from user logic to DRAM

Data Transfer

p_wr_full

from block-of-data rd/wr module to user logic

1

1=notify the user logic to pause transfer the next clock cycle until this signal is deasserted, 0=otherwise

Data Transfer

p_wr_done

from block-of-data rd/wr module to user logic

1

1=this is the last write and no more write will be accepted for this block-of-data, 0=otherwise

Signal Group

Signal Name

Direction

Bits

Description

Request Negotiation

p_rd_req

from user logic to block-of-data rd/wr module

1

1=request for read transfer (data are from DRAM to user logic), 0=otherwise

Request Negotiation

p_rd_ptr

from user logic to block-of-data rd/wr module

PKT_MEM_PTR_WIDTH

the start address of DRAM for transfer. Each unit is 16-byte piece

Request Negotiation

p_rd_ack

from block-of-data rd/wr module to user logic

1

1=the arbiter acknowledges that the read requester can proceed, 0=otherwise

Data Transfer

p_rd_rdy

from block-of-data rd/wr module to user logic

1

1=block-of-data rd/wr module has data for user logic to read, 0=otherwise

Data Transfer

p_rd_en

from user logic to block-of-data rd/wr module

1

1=user logic reads out one word of data from the block-of-data rd/wr module, 0=otherwise

Data Transfer

p_rd_data

from block-of-data rd/wr module to user logic

PKT_DATA_WIDTH

data transferred from block-of-data rd/wr module to user logic

Data Transfer

p_rd_done

from block-of-data rd/wr module to user logic

1

1=this is the last read data and no more data will be read for this block-of-data, 0=otherwise

信號名稱

位寬bits

I/O

描述

wr_vld_arb

1

I

Input_arbiter輸入有效

out_data_0

64

I

輸入的數(shù)據(jù)包的data_bus

out_ctrl_0

8

I

輸入數(shù)據(jù)包的ctrl_bus

port_num_dram

2

I

輸入信號的端口號，指明數(shù)據(jù)存放在DRAM的區(qū)域

wr_rdy_arb

1

O

寫空閑信號

port_num_rd

2

I

讀取數(shù)據(jù)包的區(qū)域

addr_vld

1

I

讀地址有效

block_num_rd

8

I

數(shù)據(jù)包存放的block的起始地址

rd_idle

1

O

讀空閑信號

in_rdy

1

I

數(shù)據(jù)輸出輸出允許信號

out_data

64

O

讀出的數(shù)據(jù)包的data_bus

out_ctrl

8

O

輸出數(shù)據(jù)包的ctrl_bus

data_vld

1

O

輸出數(shù)據(jù)有效

端口名稱

位寬  bits

I/O

描述

port_num_cam

2

In

數(shù)據(jù)寫入的CAM號，即信道號

Src_gen_seq

24

In

輸入數(shù)據(jù)包的信源號、代編號

Cam_vld

1

In

寫有效

Cam_rdy

1

Out

寫Cam準(zhǔn)備好

rd_idle

1

In

DRAM準(zhǔn)備好

block_num_rd

8

Out

讀DRAM的地址

addr_vld

1

Out

讀地址有效

port_num_rd

2

out

要讀取的DRAM的編號

Pkt_vld

1

Out

要解碼的數(shù)據(jù)包輸出有效標(biāo)志

Pkt_decoding

12

out

正在解碼的數(shù)據(jù)包的信源號、代編號

Decod_com

1

In

數(shù)據(jù)包解碼完成標(biāo)志

has_other_factor

1

Out

有另外一個(gè)解碼因子

Pkt_not_find

1

Out

所需要解碼數(shù)據(jù)包未找到

pkt_need_src_gen

12

In

解碼需要的數(shù)據(jù)包

need_pkt_vld

1

In

所需數(shù)據(jù)包有效

rd_dcod_reg_req_1

1

Out

讀解碼標(biāo)志寄存器請求

req_ack_vld_1

1

In

標(biāo)志位有效

Alredy_Decod_1

1

In

解碼標(biāo)志位

rd_dcod_src_gen_1

12

out

查詢數(shù)據(jù)包是否已經(jīng)解碼

信號名稱

位寬bits

I/O

描述

in_rdy

1

O

數(shù)據(jù)輸出輸入允許信號

out_data

64

I

輸入的數(shù)據(jù)包的data_bus

out_ctrl

8

I

輸入數(shù)據(jù)包的ctrl_bus

data_vld

1

I

輸入數(shù)據(jù)有效

rd_dcod_reg_req_0

1

O

讀取解碼標(biāo)志位請求

rd_dcod_src_gen_0

12

O

要讀取的數(shù)據(jù)包的信源號和代編號

req_ack_vld_0

1

I

輸入有效

alredy_decod_0

1

I

解碼標(biāo)志（“1”代表已經(jīng)解碼，“0”代表未解碼）

Uncod_data

64

O

未編碼數(shù)據(jù)包的數(shù)據(jù)總線

Uncod_ctrl

8

O

未編碼數(shù)據(jù)包的控制總線

Wr_vld

1

O

寫capsulation數(shù)據(jù)有效

Out_rdy

1

I

輸出capsulation允許信號

fwd_rdy

1

I

輸出fwd_sel允許信號

out_vld

1

O

輸出fwd_sel有效

pay_load

64

O

輸出fwd_sel數(shù)據(jù)（不含包頭）

eop

4

O

最后指示一個(gè)有效字節(jié)的指示

uncod

1

O

指明輸出的數(shù)據(jù)包是否編碼

src_gen_num

12

O

Decoder接收到的數(shù)據(jù)包的信源號和代的編號

len_0

16

O

被編碼的第一個(gè)數(shù)據(jù)包的有效載荷的長度

len_1

16

O

被編碼的第二個(gè)數(shù)據(jù)包的有效載荷的長度

coef_0

8

O

被編碼的第一個(gè)數(shù)據(jù)包的編碼系數(shù)

coef_1

8

O

被編碼的第二個(gè)數(shù)據(jù)包的編碼系數(shù)

hp_info_vld

1

O

輸出信息有效

encod_pkt_trans_fi

1

O

編碼數(shù)據(jù)包傳輸完畢標(biāo)志

oc_info_vld

1

I

解碼控制輸入信息有效

uncod_pkt_need

1

I

未編碼的數(shù)據(jù)包是/否解碼因子（1=是，0=否）

信號名稱

位寬bits

I/O

信號描述

fwd_rdy

1

O

輸入fwd_sel允許信號

out_vld

1

I

輸入fwd_sel有效

pay_load

64

I

輸入fwd_sel數(shù)據(jù)總線（不含包頭）

eop

4

I

最后指示一個(gè)有效字節(jié)的指示

uncod

1

I

指明輸出的數(shù)據(jù)包是否編碼

wr_req

1

O

寫RAM請求

encod_data

72

O

寫RAM的數(shù)據(jù)總線

ram_data_vld

1

O

數(shù)據(jù)有效

encod_data_eop

4

O

數(shù)據(jù)包結(jié)束標(biāo)志，指明最后一個(gè)有效字節(jié)

wr_ack

1

I

寫RAM響應(yīng)

uncod_data_vld

1

O

輸出至dcod_operation的數(shù)據(jù)有效

uncod_data_factor

64

O

輸出至dcod_operation的數(shù)據(jù)總線

uncod_data_eop

4

O

數(shù)據(jù)包結(jié)束標(biāo)志，指明最后一個(gè)有效字節(jié)

dcod_rdy

1

I

輸出至dcod_operation允許信號

fd_back_ack

1

O

接受反饋響應(yīng)

fd_back_vld

1

I

反饋數(shù)據(jù)有效標(biāo)志

fd_back_req

1

I

反饋請求

fd_back_data

64

I

反饋數(shù)據(jù)總線

fd_back_data_eop

4

I

反饋數(shù)據(jù)結(jié)束標(biāo)志，指明最后一個(gè)有效字節(jié)

信號名稱

位寬bits

I/O

信號描述

wr_req

1

I

寫RAM請求

encod_data

72

I

寫RAM的數(shù)據(jù)總線

ram_data_vld

1

I

數(shù)據(jù)有效

encod_data_eop

4

I

數(shù)據(jù)包結(jié)束標(biāo)志，指明最后一個(gè)有效字節(jié)

wr_ack

1

O

寫RAM響應(yīng)

wr_ram_num

2

I

要寫入的RAM號

info_vld

1

I

數(shù)據(jù)有效標(biāo)志

req_ram_num

1

O

讀RAM號請求

rd_ram_num

2

I

需要讀取數(shù)據(jù)的RAM號

rd_req

1

I

讀RAM請求

ram_data_eop

4

O

數(shù)據(jù)包結(jié)束標(biāo)志，指明最后一個(gè)有效字節(jié)

ram_data

72

O

讀RAM的數(shù)據(jù)總線

ram_vld

1

O

讀RAM數(shù)據(jù)有效

信號名稱

位寬bits

I/O

信號描述

Pkt_vld

1

I

要解碼的數(shù)據(jù)包輸出有效標(biāo)志

Pkt_decoding

12

I

正在解碼的數(shù)據(jù)包的信源號、代編號

Decod_com

1

O

數(shù)據(jù)包解碼完成標(biāo)志

has_other_factor

1

I

有另外一個(gè)解碼因子

Pkt_not_find

1

I

所需要解碼數(shù)據(jù)包未找到

pkt_need_src_gen

12

O

解碼需要的數(shù)據(jù)包

need_pkt_vld

1

O

所需數(shù)據(jù)包有效

src_gen_num

12

I

Decoder接收到的數(shù)據(jù)包的信源號和代的編號

len_0

16

I

被編碼的第一個(gè)數(shù)據(jù)包的有效載荷的長度

len_1

16

I

被編碼的第二個(gè)數(shù)據(jù)包的有效載荷的長度

coef_0

8

I

被編碼的第一個(gè)數(shù)據(jù)包的編碼系數(shù)

coef_1

8

I

被編碼的第二個(gè)數(shù)據(jù)包的編碼系數(shù)

hp_info_vld

1

I

輸入信息有效

encod_pkt_trans_fi

1

I

編碼數(shù)據(jù)包傳輸完畢標(biāo)志

oc_info_vld

1

O

解碼控制輸出信息有效

uncod_pkt_need

1

O

未編碼的數(shù)據(jù)包是/否解碼因子（1=是，0=否）

wr_ram_num

2

O

要寫入的RAM號

info_vld

1

O

數(shù)據(jù)有效標(biāo)志

req_ram_num

1

I

讀RAM號請求

rd_info_req

1

I

讀取解碼信息請求

dcod_info_vld

1

O

解碼信息有效

ram_num

2

O

解碼數(shù)據(jù)包的所存儲(chǔ)的RAM號

coef_mut

8

O

乘法系數(shù)

coef_div

8

O

除法系數(shù)

cap_info_req

1

I

封裝信息請求

dcod_comp

1

I

解碼封裝完成

cap_info_vld

1

O

封裝信息有效

need_feed_back

1

O

需要反饋

pkt_len

16

O

數(shù)據(jù)包長度

src_num

4

O

數(shù)據(jù)包的信源號

gen_num

8

O

數(shù)據(jù)報(bào)的代編號

信號名稱

位寬bits

I/O

信號描述

dcod_payload

64

O

解碼后的數(shù)據(jù)包的有效載荷

end_payload

4

O

數(shù)據(jù)包結(jié)束標(biāo)志，指明最后一個(gè)有效字節(jié)

payload_vld

1

O

輸出數(shù)據(jù)有效

wr_rdy

1

I

輸出數(shù)據(jù)允許信號

uncod_data_vld

1

I

輸入至dcod_operation的數(shù)據(jù)有效

uncod_data_factor

64

I

輸入至dcod_operation的數(shù)據(jù)總線

uncod_data_eop

4

I

數(shù)據(jù)包結(jié)束標(biāo)志，指明最后一個(gè)有效字節(jié)

dcod_rdy

1

O

輸入至dcod_operation允許信號

rd_ram_num

2

O

需要讀取數(shù)據(jù)的RAM號

rd_req

1

O

讀RAM請求

ram_data_eop

4

I

數(shù)據(jù)包結(jié)束標(biāo)志，指明最后一個(gè)有效字節(jié)

ram_data

72

I

讀RAM的數(shù)據(jù)總線

ram_vld

1

I

讀RAM數(shù)據(jù)有效

rd_info_req

1

O

讀取解碼信息請求

dcod_info_vld

1

I

解碼信息有效

ram_num

2

I

解碼數(shù)據(jù)包的所存儲(chǔ)的RAM號

coef_mut

8

I

乘法系數(shù)

coef_div

8

I

除法系數(shù)

信號名稱

位寬bits

I/O

信號描述

decoder_in_rdy

1

I

輸出至SRAM允許信號

decoder_in_wr

1

O

輸出有效

decoder_in_data

64

O

輸出至SRAM數(shù)據(jù)總線

decoder_in_ctrl

8

O

輸出至SRAM控制總線

set_req

1

O

置位請求

set_src_gen

12

O

需要置位的數(shù)據(jù)包（表示已經(jīng)解碼完畢）

set_info_vld

1

O

置位信息有效

set_ack

1

I

置位請求響應(yīng)

cap_info_req

1

O

封裝信息請求

dcod_comp

1

O

解碼封裝完成

cap_info_vld

1

I

封裝信息有效

need_feed_back

1

I

需要反饋

pkt_len

16

I

數(shù)據(jù)包長度

src_num

4

I

數(shù)據(jù)包的信源號

gen_num

8

I

數(shù)據(jù)報(bào)的代編號

dcod_payload

64

I

解碼后的數(shù)據(jù)包的有效載荷

end_payload

4

I

數(shù)據(jù)包結(jié)束標(biāo)志，指明最后一個(gè)有效字節(jié)

payload_vld

1

I

輸入數(shù)據(jù)有效

wr_rdy

1

O

輸入數(shù)據(jù)允許信號

fd_back_ack

1

I

接受反饋響應(yīng)

fd_back_vld

1

O

反饋數(shù)據(jù)有效標(biāo)志

fd_back_req

1

O

反饋請求

fd_back_data

64

O

反饋數(shù)據(jù)總線

fd_back_data_eop

4

O

反饋數(shù)據(jù)結(jié)束標(biāo)志，指明最后一個(gè)有效字節(jié)

Uncod_data

64

I

未編碼數(shù)據(jù)包的數(shù)據(jù)總線

Uncod_ctrl

8

I

未編碼數(shù)據(jù)包的控制總線

Wr_vld

1

I

寫capsulation數(shù)據(jù)有效

Out_rdy

1

O

輸入數(shù)據(jù)包允許信號

信號名稱

位寬bits

I/O

信號描述

decoder_in_rdy

1

O

寫SRAM控制器允許信號

decoder_in_wr

1

I

輸入有效

decoder_in_data

64

I

輸入至SRAM控制器數(shù)據(jù)總線

decoder_in_ctrl

8

I

輸入至SRAM控制器控制總線

reset_req

1

O

復(fù)位請求

reset_src_gen

12

O

需要復(fù)位的數(shù)據(jù)包（表示解碼后已發(fā)送完畢）

reset_info_vld

1

O

復(fù)位信息有效

reset_ack

1

I

復(fù)位請求響應(yīng)

dcod_data_0

64

O

輸出的IP數(shù)據(jù)包的數(shù)據(jù)總線

dcod_ctrl_0

8

O

輸出的IP數(shù)據(jù)包的控制總線

wr_vld_0

1

O

輸出有效

wr_rdy_0

1

I

發(fā)送數(shù)據(jù)允許標(biāo)志

sram_addr

19

O

Sram讀/寫地址

sram_we

1

O

Sram寫使能

sram_bw

4

O

SRAM寫入控制信號

sram_wr_data

36

O

SRAM寫數(shù)據(jù)總線

sram_rd_data

36

I

SRAM讀數(shù)據(jù)總線

sram_tri_en

1

O

SRAM寫三態(tài)控制