IMEC臺積電高通合作為III-V FinFET采用InGaAs晶體管

臺積電高通合作為III-V FinFET采用InGaAs晶體管0' />

InGaAs晶體管

元器件交易網訊 11月6日消息，據(jù)外媒 Electronicsweekly報道， IMEC宣布已為III-V FinFET 組裝300mm 制程晶圓片，該晶圓片采用了銦砷化鎵(化學符號為InGaAs)、磷化銦( indium phosphide)化合物，將容納近8%的原子晶格失配。

IMEC此次項目合作公司有TSMC、Intel、Samsung、Sony、 Qualcomm 和Toshiba。

InGaAs晶體管的優(yōu)點是能夠減少芯片尺寸，提高信息處理的速度，用作半導體材料，用于光纖通信技術，并廣泛用于探測器! 當電子在InGaAs中的傳輸速度是硅的數(shù)倍，其傳輸電流是最先進的硅晶體管的2.5倍，同時，InGaAs晶體管的尺寸僅僅為60納米。

核心CMOS高級副總裁 An Steegen說：“300mm 制程 III-V FinFET 設備將成為全球首次兼容CMOS功能的設備，這是一個激動人心的成就，因為它將有可能替代當前最先進的硅基長波長光電FinFET技術，成為下一代高容量生產可行替代方案。”

此新技術基于所捕獲到的晶體缺陷的長寬比、槽結構和外延工藝創(chuàng)新。 FinFET 晶圓設備上集成了III-V，從而顯示出優(yōu)秀性能。

IMEC邏輯研發(fā)主任 Aaron Thean表示，“ 下一步計劃將按比例縮小的硅和非硅類設備擴展結合，這將成為下一個戲劇性晶體管歷史創(chuàng)新，將打破數(shù)字CMOS領域近50年的硅晶體管設計。”(元器件交易網龍燕 譯)

外媒原文：

Imec has fabricated III-V based finfets on 300mm silicon wafers using indium gallium arsenide and indium phosphide.

Imec says the process could first be used at the 7nm node.

Partners with Imec in the project are TSMC, Intel, Samsung, Sony, Qualcomm and Toshiba.

“To our knowledge, this is the world’s first functioning CMOS compatible III-V FinFET device processed on 300mm wafers,” stated An Steegen, senior vice president core CMOS at imec, “this is an exciting accomplishment, demonstrating the technology as a viable next-generation alternative for the current state-of-the-art Si-based FinFET technology in high volume production.”

Imec’s process selectively replaces silicon fins with indium gallium arsenide (InGaAs) and indium phospide (InP), accommodating close to eight percent of atomic lattice mismatch.

The new technique is based on aspect-ratio trapping of crystal defects, trench structure, and epitaxial process innovations. The resulting III-V integrated on silicon FinFET device shows an excellent performance.

Aaron Thean, Imec’s director of the logic R&D says: “The ability to combine scaled non-silicon and silicon devices might be the next dramatic transistor face-lift, breaking almost 50 years of all-silicon reign over digital CMOS.”