模擬對數(shù)字：架起ADC到處理器的橋梁

　作為一個(gè)模擬世界的后裔，我經(jīng)常可以在走廊上聽到些評論，關(guān)于數(shù)字設(shè)計(jì)師多么不理解模擬問題。數(shù)字設(shè)計(jì)師們也毫不留情地批評模擬集成電路設(shè)計(jì)師。這兩個(gè)陣營涇渭分明，除非參與者們打破界限，一起進(jìn)入混合信號領(lǐng)域的研究。

　　對典型的模擬精神，不是所有轉(zhuǎn)換器都用相同的數(shù)據(jù)格式。一些轉(zhuǎn)換器用無符號二進(jìn)制數(shù)類型，其他轉(zhuǎn)換器使用有符號二進(jìn)制補(bǔ)碼數(shù)據(jù)。甚至更復(fù)雜的問題，轉(zhuǎn)換器輸出12位或是14位數(shù)據(jù)，還有16位輸出。還有另一種24位Δ－Σ轉(zhuǎn)換器技術(shù)。

　　先不管這些模擬設(shè)計(jì)結(jié)果的目的。對于這些轉(zhuǎn)換器而言，ADC最低有效位的位置是這些8位、16位或是32位字處理器的第0位。對模擬電路設(shè)計(jì)者來說，這具有重要意義。然而，12位轉(zhuǎn)換器的符號位是處理器的位置11。如果分配16位寬度的變量C為轉(zhuǎn)換器輸出值，假定C符號位是位置15。處理器不能從轉(zhuǎn)換器識別出負(fù)數(shù)，所有來自12位的雙極性ADC數(shù)據(jù)都是正的。因?yàn)榉栁惶幱阱e(cuò)誤位置。

　　你可以通過幾個(gè)步驟來解決這個(gè)問題。首先，讀－修改－寫步驟，將處理器寄存器中的數(shù)據(jù)移位。CPU讀取數(shù)據(jù)、移動包含數(shù)據(jù)的寄存器的位到必要的位置，然后將這些數(shù)據(jù)寫回內(nèi)存。DSP可以在一個(gè)時(shí)鐘周期內(nèi)完成移位?？刂破餍枰芏鄷r(shí)鐘周期才能完成移位的過程。如果你選用了這種控制策略，要小心緩存區(qū)的不連續(xù)性。這意味著緩存區(qū)無法辨別DMA控制器是否將新數(shù)據(jù)寫入內(nèi)存。結(jié)果，CPU將緩存區(qū)的舊數(shù)據(jù)進(jìn)行移位操作。需要記住的是，無論什么時(shí)候向左移了一位，就意味著ADC轉(zhuǎn)換結(jié)果乘了2。

　　另一種方式是在處理器循環(huán)中將數(shù)據(jù)右移。這種方式的缺點(diǎn)占用CPU并需要額外指令。另一種選擇是直接將轉(zhuǎn)換器與處理器的數(shù)據(jù)總線相連。如果你將12位轉(zhuǎn)換器的第11位與處理器總線上的第15位相連，那么符號位就會處于正確的位置。然后將數(shù)據(jù)的第11位到第14位置零來完成數(shù)據(jù)獲取，否則這些位的數(shù)據(jù)是不確定的。這種方法只適用于有并行接口。在這種方案中，基于DMA移動就不需要數(shù)據(jù)移位了。

　　使用串行端口的用戶比并行端口的用戶要幸運(yùn)的多，因?yàn)榇蟛糠痔幚砥鞯拇卸丝谔峁┙邮盏?ldquo;左移用零填充至最低有效位”或“右移符號位擴(kuò)展至最高有效位”特點(diǎn)。這種特色大大減少了CPU處理內(nèi)存中數(shù)據(jù)的工作。一些串行端口只工作在接收數(shù)據(jù)長度是2的冪時(shí)，例如16位數(shù)據(jù)長度。這些端口不能工作在12、14或是24位數(shù)據(jù)長度時(shí)。

　　模擬工程師幫助處理處理器接口問題。據(jù)我所知，處理器都是8位、16位或是32位的，我從沒聽說過12位或14位的處理器。除非所有的模擬芯片設(shè)計(jì)者突破界限，否則為轉(zhuǎn)換器設(shè)計(jì)數(shù)字接口是理所當(dāng)然的。閱讀ADC數(shù)據(jù)手冊，核對向數(shù)字接口傳輸?shù)奈坏奈恢?。如果對ADC數(shù)據(jù)接口做了初始檢查，那么你會因?yàn)殚_始的付出獲得更多成功。

　　英文原文：

　　Analog versus digital: Bridging the ADC-to-processor divide

　　Don’t take things for granted when you are designing the digital interface to a converter. Read the ADC data sheet and verify the bit positions in the transmission across the digital interface.

　　By Bonnie Baker -- EDN, 5/10/2007

　　As an analog-world descendant, I always hear comments in the hallway about how digital designers don’t really understand analog issues. Digital designers will go so far as to unsympathetically say the same about analog-IC designers. There is no bridge between these two camps unless the participants ride the fence and enter the mixed-signal domain together.

　　True to the analog spirit, not all data converters use the same digital format. Some converters use unsigned-binary-data types; other converters use two’s-complement signed data. To even further complicate matters, some converters produce 12- or 14-bit output words, and others produce 16-bit output words. Yet another technology is the 24-bit delta-sigma converter.

　　Forget the reasons for these analog-design decisions. With all of these converters, the location of the ADC LSB is in the processor’s 0-bit location within the 8-, 16-, or 32-bit word. This situation makes perfect sense to an analog designer. However, the signed-bit of a 12-bit converter resides in position 11 in the processor. If you assign a 16-bit-wide C variable to the converter’s output word, C assumes that the sign bit is in position 15. The processor does not recognize a negative number from the converter and assumes that all codes from the 12-bit, bipolar-in ADC are positive. This situation occurs because the signed bit is in the wrong position.

　　You can approach this problem in several ways. The first, a read-modify-write approach, shifts data in the processor register. The CPU reads the data, shifts the bits in the register containing the data by the necessary amount of bit positions, and writes the data back to memory. A DSP can complete this shift with one cycle. A controller requires many cycles for this shift process. If this strategy is the one you choose, be careful of cache incoherency. Cache incoherency means that the cache is unaware that the DMA controller has placed new words in memory. As a result, the CPU instead shifts the old contents of the cache. It is important to remember that whenever you implement a bit shift to the left, you multiply the ADC results by two.

　　Another option is to shift the data into the right position in a processor loop. On the downside, this approach uses the CPU and requires additional MIPS. Another alternative is to directly connect the converter to the processor’s data bus. If you connect bit 11 of the 12-bit converter to bit 15 of the processor’s data bus, the sign bit will then be in the right place. Complete the data-acquisition task by zeroing register bits 11 through 14. Otherwise, these bits are indeterminate. This approach is possible only with parallel interfaces. In this scenario, the DMA-based transfer need not shift data later on.

　　Serial-port users are more fortunate than parallel-port users because most of the serial ports in processors offer the receiving feature of “left justify and zero fill LSBs” or “right justify and sign-extend MSBs.” This feature significantly reduces the amount of work the CPU must perform once the data is in memory, with one drawback. Some serial ports work only if the received word length is a power of two, such as a 16-bit word length. This receiving feature does not work with 12-, 14-, or 24-bit values.

　　Analog designers can help with the processor-interface problem. All the processors I know about have 8-, 16- or 32-bit data types, but I have never heard of a 12- or 14-bit data type. Until all of the analog-chip designers take the leap and straddle the fence, don’t take things for granted when you are designing the digital interface to a converter. Read the ADC data sheet and verify the bit positions in the transmission across the digital interface. If you do this initial examination of the ADC’s documented digital interface, you will be more successful with your first spin on the design.