DDR3 PCB設(shè)計時鐘信號布線規(guī)則

參數(shù)定義信號組（Signal Group）Clock – CLK[5:0] and CLK#[5:0]拓?fù)?Topology)點到點差分對Differential Pair Point-to-point走線層表層（A）參考平面(Reference Plane)地平面差分信號阻抗（Differential Mode Impedance）80Ω+/-10%(80Ω)與非DDR3 信號的最小間距（Minimum Isolation Spacing to non-DDR3 Signals）25mil與其他DDR3 信號組的最小間距（Minimum Isolation Spacing to other-DDR3 Signal Groups）20mil封裝長度的范圍（P1, Package Length Range）731mil ~ 740mil 750mil ~ 759mil L1(Microstrip)(Fanout length segment)扇出差分對線寬/線距：4mil/4mil與其他DDR3 信號間距：4milL1 的長度應(yīng)盡量短L2(Microstrip)與其他DDR3 信號間距：數(shù)據(jù)>20mil (trace-to-trace spacing > 4H)地址>20mil (trace-to-trace spacing > 4H)總的板級走線長度(Total Motherboard Length Limits, L1+L2)Max = 3000mil信號的總長度限制-P1+L1+L2Max = 4000mil最大的過孔數(shù)（Maximum Recommended Via Count）2 個，信號換層時在信號線附近增加電源或地的過孔SCK 與SCK#的長度匹配（SCK to SCK# Length Matching）(Total length including package)總長度的最大差別 < 5mil時鐘對與時鐘對的長度匹配（Clock-to-Clock Total Length Matching）到相同 DIMM 的總長度的最大差別：+/-10mil