verilog PS2鍵盤(pán)解碼程序
除了頂層模塊,三個(gè)底層模塊分別為PS/2傳輸處理模塊、串口傳輸模塊以及串口波特率選擇模塊(下面只給出頂層模塊和PS/2傳輸處理模塊的verilog代碼)。
module ps2_key(clk,rst_n,ps2k_clk,ps2k_data,rs232_tx);
input clk; //50M時(shí)鐘信號(hào)
input rst_n; //復(fù)位信號(hào)
input ps2k_clk; //PS2接口時(shí)鐘信號(hào)
input ps2k_data; //PS2接口數(shù)據(jù)信號(hào)
output rs232_tx; // RS232發(fā)送數(shù)據(jù)信號(hào)
wire[7:0] ps2_byte; // 1byte鍵值
wire ps2_state; //按鍵狀態(tài)標(biāo)志位
wire bps_start; //接收到數(shù)據(jù)后,波特率時(shí)鐘啟動(dòng)信號(hào)置位
wire clk_bps; // clk_bps的高電平為接收或者發(fā)送數(shù)據(jù)位的中間采樣點(diǎn)
ps2scan ps2scan( .clk(clk), //按鍵掃描模塊
.rst_n(rst_n),
.ps2k_clk(ps2k_clk),
.ps2k_data(ps2k_data),
.ps2_byte(ps2_byte),
.ps2_state(ps2_state)
);
speed_select speed_select( .clk(clk),
.rst_n(rst_n),
.bps_start(bps_start),
.clk_bps(clk_bps)
);
my_uart_tx my_uart_tx( .clk(clk),
.rst_n(rst_n),
.clk_bps(clk_bps),
.rx_data(ps2_byte),
.rx_int(ps2_state),
.rs232_tx(rs232_tx),
.bps_start(bps_start)
);
Endmodule
module ps2scan(clk,rst_n,ps2k_clk,ps2k_data,ps2_byte,ps2_state);
input clk; //50M時(shí)鐘信號(hào)
input rst_n; //復(fù)位信號(hào)
input ps2k_clk; //PS2接口時(shí)鐘信號(hào)
input ps2k_data; //PS2接口數(shù)據(jù)信號(hào)
output[7:0] ps2_byte; // 1byte鍵值,只做簡(jiǎn)單的按鍵掃描
output ps2_state; //鍵盤(pán)當(dāng)前狀態(tài),ps2_state=1表示有鍵被按下
//------------------------------------------
reg ps2k_clk_r0,ps2k_clk_r1,ps2k_clk_r2; //ps2k_clk狀態(tài)寄存器
//wire pos_ps2k_clk; // ps2k_clk上升沿標(biāo)志位
wire neg_ps2k_clk; // ps2k_clk下降沿標(biāo)志位
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
ps2k_clk_r0 <= 1'b0;
ps2k_clk_r1 <= 1'b0;
ps2k_clk_r2 <= 1'b0;
end
else begin //鎖存狀態(tài),進(jìn)行濾波
ps2k_clk_r0 <= ps2k_clk;
ps2k_clk_r1 <= ps2k_clk_r0;
ps2k_clk_r2 <= ps2k_clk_r1;
end
end
assign neg_ps2k_clk = ~ps2k_clk_r1 & ps2k_clk_r2; //下降沿
//------------------------------------------
reg[7:0] ps2_byte_r; //PC接收來(lái)自PS2的一個(gè)字節(jié)數(shù)據(jù)存儲(chǔ)器
reg[7:0] temp_data; //當(dāng)前接收數(shù)據(jù)寄存器
reg[3:0] num; //計(jì)數(shù)寄存器
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
num <= 4'd0;
temp_data <= 8'd0;
end
else if(neg_ps2k_clk) begin //檢測(cè)到ps2k_clk的下降沿
case (num)
4'd0: num <= num+1'b1;
4'd1: begin
num <= num+1'b1;
temp_data[0] <= ps2k_data; //bit0
end
4'd2: begin
num <= num+1'b1;
temp_data[1] <= ps2k_data; //bit1
end
4'd3: begin
num <= num+1'b1;
temp_data[2] <= ps2k_data; //bit2
end
4'd4: begin
num <= num+1'b1;
temp_data[3] <= ps2k_data; //bit3
end
4'd5: begin
num <= num+1'b1;
temp_data[4] <= ps2k_data; //bit4
end
4'd6: begin
num <= num+1'b1;
temp_data[5] <= ps2k_data; //bit5
end
4'd7: begin
num <= num+1'b1;
temp_data[6] <= ps2k_data; //bit6
end
4'd8: begin
num <= num+1'b1;
temp_data[7] <= ps2k_data; //bit7
end
4'd9: begin
num <= num+1'b1; //奇偶校驗(yàn)位,不做處理
end
4'd10: begin
num <= 4'd0; // num清零
end
default: ;
endcase
end
end
reg key_f0; //松鍵標(biāo)志位,置1表示接收到數(shù)據(jù)8'hf0,再接收到下一個(gè)數(shù)據(jù)后清零
reg ps2_state_r; //鍵盤(pán)當(dāng)前狀態(tài),ps2_state_r=1表示有鍵被按下
always @ (posedge clk or negedge rst_n) begin //接收數(shù)據(jù)的相應(yīng)處理,這里只對(duì)1byte的鍵值進(jìn)行處理
if(!rst_n) begin
key_f0 <= 1'b0;
ps2_state_r <= 1'b0;
end
else if(num==4'd10) begin //剛傳送完一個(gè)字節(jié)數(shù)據(jù)
if(temp_data == 8'hf0) key_f0 <= 1'b1;
else begin
if(!key_f0) begin //說(shuō)明有鍵按下
ps2_state_r <= 1'b1;
ps2_byte_r <= temp_data; //鎖存當(dāng)前鍵值
end
else begin
ps2_state_r <= 1'b0;
key_f0 <= 1'b0;
end
end
end
end
reg[7:0] ps2_asci; //接收數(shù)據(jù)的相應(yīng)ASCII碼
always @ (ps2_byte_r) begin
case (ps2_byte_r) //鍵值轉(zhuǎn)換為ASCII碼,這里做的比較簡(jiǎn)單,只處理字母
8'h15: ps2_asci <= 8'h51; //Q
8'h1d: ps2_asci <= 8'h57; //W
8'h24: ps2_asci <= 8'h45; //E
8'h2d: ps2_asci <= 8'h52; //R
8'h2c: ps2_asci <= 8'h54; //T
8'h35: ps2_asci <= 8'h59; //Y
8'h3c: ps2_asci <= 8'h55; //U
8'h43: ps2_asci <= 8'h49; //I
8'h44: ps2_asci <= 8'h4f; //O
8'h4d: ps2_asci <= 8'h50; //P
8'h1c: ps2_asci <= 8'h41; //A
8'h1b: ps2_asci <= 8'h53; //S
8'h23: ps2_asci <= 8'h44; //D
8'h2b: ps2_asci <= 8'h46; //F
8'h34: ps2_asci <= 8'h47; //G
8'h33: ps2_asci <= 8'h48; //H
8'h3b: ps2_asci <= 8'h4a; //J
8'h42: ps2_asci <= 8'h4b; //K
8'h4b: ps2_asci <= 8'h4c; //L
8'h1z: ps2_asci <= 8'h5a; //Z
8'h22: ps2_asci <= 8'h58; //X
8'h21: ps2_asci <= 8'h43; //C
8'h2a: ps2_asci <= 8'h56; //V
8'h32: ps2_asci <= 8'h42; //B
8'h31: ps2_asci <= 8'h4e; //N
8'h3a: ps2_asci <= 8'h4d; //M
default: ;
endcase
end
assign ps2_byte = ps2_asci;
assign ps2_state = ps2_state_r;
endmodule