基于MCF51CN128設(shè)計(jì)的以太網(wǎng)連接參考方案

The MCF51CN128 features the following functional units:

• 32-bit ColdFire V1 Central Processing Unit (CPU)

– Up to 50.33 MHz ColdFire CPU from 3.6 V to 3.0 V, up to 40 MHz CPU from 3.0 V to 2.1 V, and up to 20 MHz CPU from 2.1 V to 1.8 V across temperature range of –40 °C to 85 °C

– Provides 0.94 Dhrystone 2.1 MIPS per MHz performance when running from internal RAM (0.76 DMIPS/MHz from flash)

– ColdFire Instruction Set Revision C (ISA_C)

– Support for up to 45 peripheral interrupt requests and 7 software interrupts

• On-Chip Memory

– 128 KB Flash, 24 KB RAM

– Flash read/program/erase over full operating voltage and temperature

– On-chip memory aliased to create a contiguous memory space with off-chip memory

– Security circuitry to prevent unauthorized access to Peripherals, RAM, and flash contents

• Ethernet

– FEC—10/100 BASE-T/TX, bus-mastering fast Ethernet controller with direct memory access (DMA); supports half or full duplex; operation is limited to 3.0 V to 3.6 V

– MII—media independent interface to connect Ethernet controller to external PHY; includes output clock for external PHY

• External Bus

– Mini-FlexBus—Multi-function external bus interface; supports up to 1 MB memories, gate-array logic, simple slave device or glueless interfaces to standard chip-selected asynchronous memories

– Programmable options: access time per chip select, burst and burst-inhibited transfers per chip select, transfer direction, and address setup and hold times

• Power-Saving Modes

– Two low-power stop modes, one of which allows limited use of some peripherals (ADC, KBI, RTC)

– Reduced-power wait mode shuts off CPU and allows full use of all peripherals; FEC can remain active and conduct DMA transfers to RAM and assert an interrupt to wake up the CPU upon completion

– Low-power run and wait modes allow peripherals to run while the voltage regulator is in standby

– Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents

– Low-power external oscillator that can be used in stop3 mode to provide accurate clock source to active peripherals

– Low-power real-time counter for use in run, wait, and stop modes with internal and external clock sources

– 6 μs typical wake-up time from stop3 mode

– Pins and clocks to peripherals not available in smaller packages are automatically disabled for reduced current consumption; no user interaction is needed

• Clock Source Options

– Oscillator (XOSC) — Loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 25 MHz

– Multi-Purpose Clock Generator (MCG) — Flexible clock source module with either frequency-locked-loop (FLL) or phase-lock loop (PLL) clock options. FLL can be controlled by internal or external reference and includes precision trimming of internal reference, allowing 0.2% resolution and 2% deviation over temperature and voltage. PLL derives a higher accuracy clock source derived by an external reference

• System Protection

– Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock

– Low-voltage detection with reset or interrupt; selectable trip points

– Illegal opcode and illegal address detection with programmable reset or exception response

– Flash block protection

• Development Support

– Single-wire background debug module (BDM) interface; supports same electrical interface used by the S08, 9S12, and 9S12x families debug modules

– 4 PC plus 2 address (optional data) breakpoint registers with programmable 1- or 2-level trigger response

– 64-entry processor status and debug data trace buffer with programmable start/stop conditions

• Peripherals

– ADC—Up to 12 channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V

– SCI—Three modules with optional 13-bit break

– SPI—Two interfaces with full-duplex or single-wire bi-directional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting

– IIC—Two IICs with up to 100 kbps with maxmimum bus loading; multi-master operation; programmable slave address; interrupt-driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing

– TPM—Two 3-channel, 16-bit resolution modules; selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel

– RTC—8-bit modulus counter with binary- or decimal-based prescaler; external clock source for precise time base, time-of-day, calendar- or task-scheduling functions; free-running on-chip low-power oscillator (1 kHz) for cyclic wake-up without external components; runs in all MCU modes

– MTIM—Two 8-bit resolution modulo timers with 8-bit prescaler

• Input/Output

– Up to 70 general-purpose input/output (GPIO) pins, all with pin mux controls to select alternate functions

– 16 keyboard interrupt (KBI) pins with selectable polarity

–        Hysteresis and configurable pull-up device or input filtering on all input pins; configurable slew rate and drive strength on all output pins 16 Rapid GPIO pins connected to the CPU’s high-speed local bus with set, clear, and toggle functionality (PTD and PTF)

MCF51CN128目標(biāo)應(yīng)用:

Building control

Industrial operator interfaces

Consumer and industrial appliances

Medical monitoring and instrumentation

Point-of-sale and courier systems

Security and building control systems

圖1.MCF51CN128方框圖

RDMCF51CN128: Serial to Ethernet Bridge

The most common use of this reference design will be to integrate old MCU projects to the internet. The connection between these legacy microcontrollers will be by SCI and SPI. The MCU used is the MCF51CN128. As a second goal, customers don’t need to know about ETH, or in certain cases, a little knowledge will be required, though enough information is provided for customer education in Lasko Ethernet TCP/IP implementation.

圖2.MCF51CN128以太網(wǎng)連接參考設(shè)計(jì)外形圖[!--empirenews.page--]

以太網(wǎng)連接參考設(shè)計(jì)主要特性:

The following list shows some of the reference design features:

–        Hardware:

Ethernet Minimal System in 1.15’’x1.55’’

RTOS+TCP/IP highly coupled and customized for a very small memory footprint

Webserver supporting HTTP 2.0

File System (FAT16) thru uSD socket

Bridges to UART, SPI and IIC to Ethernet easily

Serial Header that allows to use signals as needed

Sensors (SPI and I2C) already on board

–        Sofware:

lwIP 1.3.0 + FreeRTOS v5.3.0

Layered Software for easy migration and upgrade of SW drivers

The following reference design implements:

Web Server

Email Client

FTP Server

SD card driver

FAT16 file system

Serial Bridge

圖3.以太網(wǎng)連接參考設(shè)計(jì)電路圖(1)

圖4.以太網(wǎng)連接參考設(shè)計(jì)電路圖(2)

圖5.以太網(wǎng)連接參考設(shè)計(jì)電路圖(3)

圖6.以太網(wǎng)連接參考設(shè)計(jì)電路圖(4)