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[導(dǎo)讀]Ingenient和TI合作的便攜式媒體播放器(PMP)設(shè)計解決方案采用基于DaVinci技術(shù)的處理器TMS320DM644x,提供高效率高質(zhì)量的多媒體,適用于高端數(shù)字媒體產(chǎn)品.解決方案還包括TI的AIC33立體聲編譯碼器(CODEC),TVP5160視頻譯碼

Ingenient和TI合作的便攜式媒體播放器(PMP)設(shè)計解決方案采用基于DaVinci技術(shù)的處理器TMS320DM644x,提供高效率高質(zhì)量的多媒體,適用于高端數(shù)字媒體產(chǎn)品.解決方案還包括TI的AIC33立體聲編譯碼器(CODEC),TVP5160視頻譯碼器和TPS62/TPS76系列電源調(diào)整器.

Portable Media Player Based on DaVinci™Technology
Today, portable media player (PMP) functionality has become a must-have for portable DTV receivers used in DVB-H/T, ISDB-T, T-DMB and VOD products.

Ingenient has been at the forefront of this requirement by enabling various leading companies to introduce successful battery-powered PMPs into today’s marketplace.As a primary solution provider, Ingenient offers complete solutions that facilitate extensive digital movie, music and photo playback and recording.

The MP512x-PMP-DM644x product design solution utilizes the TMS320DM644x processor based on DaVinci™ technology. This solution provides power-efficient, high-quality multimedia, giving Ingenient’s customers the capability to make highend digital media products without sacrificing portability or power. The solution also includes TI AIC33 stereo codec, TVP5160 video decoder and TPS62/TPS76 series power regulations.

下圖為PMP方框圖:



功能描述:

User-friendly graphical interface for easy operation

Record video and synchronized audio directly from TV, VCR, DVD player or video camera

plus still images

Record audio directly from any stereo or mono audio source including microphone

Download and store digital video, audio and images from PC over USB 2.0 or 802.11 b/g

Play movies on an integral LCD screen and headphones or on a TV monitor and speakers

Display photos with or without music in still or Photo Show mode

View and record DVB-H, T-DMB or ISDB-T broadcast content

Personal navigation and broadcast content viewing.
所選用的元件:

TMS320DM644x processor

TLV320AIC33 (audio codec)

TVP5160 (video codec)

TPS62xxx (power regulators)

TPS76xxx (power regulators)

開發(fā)板:

MP4900-BRD-DM644x-10
Schematics
Gerber files

軟件:

Multimedia framework
Integrated multimedia operational modes and functions
Operating systems
WinCE 5.0
Linux 2.6.15
Video pre/post processing
Audio equalization and audio post processing
Audio/video/communications hardware drivers
AIC33
TVP5160
USB 2.0 Host/Client
LAN
802.11g
Video codecs
H.264
MPEG4 SP/ASP
MPEG2
MPEG1
DivX (home theater profile)
XviD
Windows Media® Video 7/8/9
Audio codecs
Dolby digital (AC-3)
MPEG2 AAC LC
MPEG4 AAC LC
MPEG4 AAC HE (version 1.0 and 2.0)
MPEG1/2 layer 1 and 2
MPEG1/2 layer 3 (including MP3 2.5)
Windows Media® Audio
Ogg Vorbis
Speech codecs
G.711
G.722/722.1
G.723.1
G.726
G.729AB
GSM-AMR

人門文件:

API manuals
User guides
Example code
Release notes
Email/phone support
Ingenient Services
Integration
Customization
Solution design

下面是TMS320DM6443的性能介紹:

The TMS320DM6443 (also referenced as DM6443) leverages TIs Davinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6443 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the DM6443 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S MPU core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates:

A coprocessor 15 (CP15) and protection module

Data and program Memory Management Units (MMUs) with table look-aside buffers.

Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000 DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.
With performance of up to 4752 million instructions per second (MIPS) at a clock rate of 594 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2376 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4752 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6443 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6443 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.



來源:零八我的愛0次

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