當(dāng)前位置:首頁(yè) > 單片機(jī) > 單片機(jī)
[導(dǎo)讀]  Today I implement "Hello World" on PIC32MZ EC starter kit. The application of "Hello World" only lights up a LED. There are three LEDs on the starter kit board -- LED1 and LED2 and LED3. At the mo

  Today I implement "Hello World" on PIC32MZ EC starter kit. The application of "Hello World" only lights up a LED. There are three LEDs on the starter kit board -- LED1 and LED2 and LED3. At the moment, I only light LED1 on RH0.


Every PIC application has to set several configuration bits, PIC32 is no exception. So we start with configuration bits. The following is the configuration bits I set for the "Hello world" application.



// PIC32MZ2048ECH144 Configuration Bit Settings


// 'C' source line config statements


#include


// DEVCFG3  BFFFFFFF

// USERID = No Setting

#pragma config FMIIEN = ON // Ethernet RMII/MII Enable (MII Enabled) // in MII Mode, you need a 25MHz XTAL, in RMII Mode, need a 50MHz Clock.

#pragma config FETHIO = ON // Ethernet I/O Pin Select (Default Ethernet I/O)

#pragma config PGL1WAY = ON // Permission Group Lock One Way Configuration (Allow only one reconfiguration)

#pragma config PMDL1WAY = ON // Peripheral Module Disable Configuration (Allow only one reconfiguration)

#pragma config IOL1WAY = ON // Peripheral Pin Select Configuration (Allow only one reconfiguration)

#pragma config FUSBIDIO = OFF // USB USBID Selection (Controlled by Port Function)


// DEVCFG2  7FF9B11A

#pragma config FPLLIDIV = DIV_3 // System PLL Input Divider (3x Divider)

#pragma config FPLLRNG = RANGE_5_10_MHZ // System PLL Input Range (5-10 MHz Input)

#pragma config FPLLICLK = PLL_POSC // System PLL Input Clock Selection (POSC is input to the System PLL)

#pragma config FPLLMULT = MUL_50 // System PLL Multiplier (PLL Multiply by 50)

#pragma config FPLLODIV = DIV_2 // System PLL Output Clock Divider (2x Divider)

#pragma config UPLLFSEL = FREQ_24MHZ // USB PLL Input Frequency Selection (USB PLL input is 24 MHz)

#pragma config UPLLEN = OFF // USB PLL Enable (USB PLL is disabled)


// DEVCFG1  7F7F3839

#pragma config FNOSC = SPLL // Oscillator Selection Bits (System PLL)

#pragma config DMTINTV = WIN_127_128 // DMT Count Window Interval (Window/Interval value is 127/128 counter value)

#pragma config FSOSCEN = OFF // Secondary Oscillator Enable (Disable SOSC)

#pragma config IESO = OFF // Internal/External Switch Over (Disabled)

#pragma config POSCMOD = EC // Primary Oscillator Configuration (External clock mode)

#pragma config OSCIOFNC = ON // CLKO Output Signal Active on the OSCO Pin (Enabled)

#pragma config FCKSM = CSDCMD // Clock Switching and Monitor Selection (Clock Switch Disabled, FSCM Disabled)

#pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576)

#pragma config WDTSPGM = STOP // Watchdog Timer Stop During Flash Programming (WDT stops during Flash programming)

#pragma config WINDIS = NORMAL // Watchdog Timer Window Mode (Watchdog Timer is in non-Window mode)

#pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled)

#pragma config FWDTWINSZ = WINSZ_25 // Watchdog Timer Window Size (Window size is 25%)

#pragma config DMTCNT = DMT31 // Deadman Timer Count Selection (2^31 (2147483648))

#pragma config FDMTEN = OFF // Deadman Timer Enable (Deadman Timer is disabled)


// DEVCFG0  FFFFFFF7

#pragma config DEBUG = OFF // Background Debugger Enable (Debugger is disabled)

#pragma config JTAGEN = ON // JTAG Enable (JTAG Port Enabled)

#pragma config ICESEL = ICS_PGx2 // ICE/ICD Comm Channel Select (Communicate on PGEC2/PGED2)

#pragma config TRCEN = ON // Trace Enable (Trace features in the CPU are enabled)

#pragma config BOOTISA = MIPS32 // Boot ISA Selection (Boot code and Exception code is MIPS32)

#pragma config FECCCON = OFF_UNLOCKED // Dynamic Flash ECC Configuration (ECC and Dynamic ECC are disabled (ECCCON bits are writable))

#pragma config FSLEEP = OFF // Flash Sleep Mode (Flash is powered down when the device is in Sleep mode)

#pragma config DBGPER = ALLOW_PG2 // Debug Mode CPU Access Permission (Allow CPU access to Permission Group 2 permission regions)

#pragma config EJTAGBEN = NORMAL // EJTAG Boot (Normal EJTAG functionality)


// DEVCP0

#pragma config CP = OFF // Code Protect (Protection Disabled)


// SEQ0


// DEVADC1


// DEVADC2


// DEVADC3


// DEVADC4


// DEVADC5


Please remember a configuration bit can only be programmed logic 0, the unprogrammed state is logic 1, and device configuration bits may vary according to hardware and software. An important point is that PLL must output between 350 and 700 MHz. The PLL output is 400MHz in my configuration. Anyway, above configuration words work to me till now.


  Configuration bits is set, then we will continue with main function. The main function is very simple, just toggle H0 to logic 1. But before we do that, we should change the direction of H0 to be output. For 8-bit PIC, we usually code that like below.


TRISHbits.TRISH0 = 0; // clear TRISH bit0, H0 to be output

PORTHbits.RH0 = 1; // set PORTH bit0

  But for PIC32, below code is recommended (use LATx to write IO, PORTx to read IO).


TRISHbits.TRISH0 = 0;

LATHbits.LATH0 = 0;

  Every PIC32 I/O module register has a corresponding CLR(clear), SET(set) and INV(invert) register designed to provide fast atomic bit manipulations, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as '1' as modified. Bits specified as '0' are not modified.


  So the above implemention has alternative option


TRISHCLR = (1<<0); // TRISH bit0 clear

LATHSET = (1<<0); // LATH bit0 set '1'

It almost like


TRISH &= 0xFFFFFFFE;

LATH |= 0x00000001;

  But it performs faster and more effectively than above. So far, there is an important point not to clarify. The I/O port H0 mixes with analog feature, and the analog feature should be disabled. For this point, PIC32MZ is different than PIC32MX. On PIC32MX devices, the analog function of an I/O pin was determined by the PCFGx bit in AD1PCFG register. On PIC32MZ devices, the analog selection function has been moved into a separate register on each I/O port. Clear ANSxy (ANSELx) bit to select digital mode.


  Finally, the main code of "Hello world" is


#include


#include "ConfigurationBits.h"


//#define LED_IOCTL() TRISHbits.TRISH0 = 0

//#define LED_SETON() LATHbits.LATH0 = 1

//#define LED_OPEN() ANSELHbits.ANSH0 = 0


//#define LED_IOCTL() TRISH &= 0xFFFFFFFE

//#define LED_SETON() LATH |= 0x00000001

//#define LED_OPEN() ANSELH &= 0xFFFFFFFE


#define LED_IOCTL() TRISHCLR = (1<<0)

#define LED_SETON() LATHSET = (1<<0)

#define LED_OPEN() ANSELH &= 0xFFFFFFFE


void main()

{

LED_OPEN();

LED_IOCTL();

LED_SETON();

while (1)

{

; // do nothing

}

}


本站聲明: 本文章由作者或相關(guān)機(jī)構(gòu)授權(quán)發(fā)布,目的在于傳遞更多信息,并不代表本站贊同其觀點(diǎn),本站亦不保證或承諾內(nèi)容真實(shí)性等。需要轉(zhuǎn)載請(qǐng)聯(lián)系該專欄作者,如若文章內(nèi)容侵犯您的權(quán)益,請(qǐng)及時(shí)聯(lián)系本站刪除。
換一批
延伸閱讀

9月2日消息,不造車的華為或?qū)⒋呱龈蟮莫?dú)角獸公司,隨著阿維塔和賽力斯的入局,華為引望愈發(fā)顯得引人矚目。

關(guān)鍵字: 阿維塔 塞力斯 華為

倫敦2024年8月29日 /美通社/ -- 英國(guó)汽車技術(shù)公司SODA.Auto推出其旗艦產(chǎn)品SODA V,這是全球首款涵蓋汽車工程師從創(chuàng)意到認(rèn)證的所有需求的工具,可用于創(chuàng)建軟件定義汽車。 SODA V工具的開(kāi)發(fā)耗時(shí)1.5...

關(guān)鍵字: 汽車 人工智能 智能驅(qū)動(dòng) BSP

北京2024年8月28日 /美通社/ -- 越來(lái)越多用戶希望企業(yè)業(yè)務(wù)能7×24不間斷運(yùn)行,同時(shí)企業(yè)卻面臨越來(lái)越多業(yè)務(wù)中斷的風(fēng)險(xiǎn),如企業(yè)系統(tǒng)復(fù)雜性的增加,頻繁的功能更新和發(fā)布等。如何確保業(yè)務(wù)連續(xù)性,提升韌性,成...

關(guān)鍵字: 亞馬遜 解密 控制平面 BSP

8月30日消息,據(jù)媒體報(bào)道,騰訊和網(wǎng)易近期正在縮減他們對(duì)日本游戲市場(chǎng)的投資。

關(guān)鍵字: 騰訊 編碼器 CPU

8月28日消息,今天上午,2024中國(guó)國(guó)際大數(shù)據(jù)產(chǎn)業(yè)博覽會(huì)開(kāi)幕式在貴陽(yáng)舉行,華為董事、質(zhì)量流程IT總裁陶景文發(fā)表了演講。

關(guān)鍵字: 華為 12nm EDA 半導(dǎo)體

8月28日消息,在2024中國(guó)國(guó)際大數(shù)據(jù)產(chǎn)業(yè)博覽會(huì)上,華為常務(wù)董事、華為云CEO張平安發(fā)表演講稱,數(shù)字世界的話語(yǔ)權(quán)最終是由生態(tài)的繁榮決定的。

關(guān)鍵字: 華為 12nm 手機(jī) 衛(wèi)星通信

要點(diǎn): 有效應(yīng)對(duì)環(huán)境變化,經(jīng)營(yíng)業(yè)績(jī)穩(wěn)中有升 落實(shí)提質(zhì)增效舉措,毛利潤(rùn)率延續(xù)升勢(shì) 戰(zhàn)略布局成效顯著,戰(zhàn)新業(yè)務(wù)引領(lǐng)增長(zhǎng) 以科技創(chuàng)新為引領(lǐng),提升企業(yè)核心競(jìng)爭(zhēng)力 堅(jiān)持高質(zhì)量發(fā)展策略,塑強(qiáng)核心競(jìng)爭(zhēng)優(yōu)勢(shì)...

關(guān)鍵字: 通信 BSP 電信運(yùn)營(yíng)商 數(shù)字經(jīng)濟(jì)

北京2024年8月27日 /美通社/ -- 8月21日,由中央廣播電視總臺(tái)與中國(guó)電影電視技術(shù)學(xué)會(huì)聯(lián)合牽頭組建的NVI技術(shù)創(chuàng)新聯(lián)盟在BIRTV2024超高清全產(chǎn)業(yè)鏈發(fā)展研討會(huì)上宣布正式成立。 活動(dòng)現(xiàn)場(chǎng) NVI技術(shù)創(chuàng)新聯(lián)...

關(guān)鍵字: VI 傳輸協(xié)議 音頻 BSP

北京2024年8月27日 /美通社/ -- 在8月23日舉辦的2024年長(zhǎng)三角生態(tài)綠色一體化發(fā)展示范區(qū)聯(lián)合招商會(huì)上,軟通動(dòng)力信息技術(shù)(集團(tuán))股份有限公司(以下簡(jiǎn)稱"軟通動(dòng)力")與長(zhǎng)三角投資(上海)有限...

關(guān)鍵字: BSP 信息技術(shù)
關(guān)閉
關(guān)閉