i2c驅(qū)動(dòng)之i2c-s3c2410.c

#include
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/* i2c controller state */
//i2c控制器狀態(tài)
enum s3c24xx_i2c_state {
STATE_IDLE,
STATE_START,
STATE_READ,
STATE_WRITE,
STATE_STOP
};

struct s3c24xx_i2c {
spinlock_tlock;
/*
在數(shù)據(jù)發(fā)送函數(shù)s3c24xx_i2c_doxfer中wait_event_timeout，
在數(shù)據(jù)發(fā)送完成函數(shù)s3c24xx_i2c_master_complete中wake_up
*/
wait_queue_head_twait;
unsigned intsuspended:1;

struct i2c_msg*msg;//管理收發(fā)數(shù)據(jù)的結(jié)構(gòu)體
unsigned intmsg_num;//待收發(fā)msg的數(shù)目
unsigned intmsg_idx;//當(dāng)前正在處理的msg在msg_num個(gè)msg中的序號(hào)
//每個(gè)msg都管理一段內(nèi)存，msg_ptr是這段內(nèi)存空間的偏移。
unsigned intmsg_ptr;
//在數(shù)據(jù)寫入IICDS后的等待時(shí)間，在數(shù)據(jù)寫入前SCL保持低電平，寫入后
//釋放，這個(gè)狀態(tài)的建立需要一定的時(shí)間。
unsigned inttx_setup;
unsigned intirq;

enum s3c24xx_i2c_statestate;
//保存上一次通過clk_get_rate(i2c->clk);獲取的頻率。
//當(dāng)本次獲取的頻率與clkrate不等時(shí)說明系統(tǒng)時(shí)鐘改變。
unsigned longclkrate;

void __iomem*regs;
struct clk*clk;
struct device*dev;
struct resource*ioarea;//
struct i2c_adapteradap;//適配器結(jié)構(gòu)體，這整個(gè)結(jié)構(gòu)體都是對(duì)它的包裝。

#ifdef CONFIG_CPU_FREQ
struct notifier_blockfreq_transition;//通知鏈
#endif
};

/* default platform data removed, dev should always carry data. */

/* s3c24xx_i2c_is2440()
*
* return true is this is an s3c2440
*/
//如果是s3c2440則返回1
static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
{
struct platform_device *pdev = to_platform_device(i2c->dev);

return !strcmp(pdev->name, "s3c2440-i2c");
}

/* s3c24xx_i2c_master_complete
*
* complete the message and wake up the caller, using the given return code,
* or zero to mean ok.
*/

static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
{
dev_dbg(i2c->dev, "master_complete %dn", ret);

i2c->msg_ptr = 0;
i2c->msg = NULL;
i2c->msg_idx++;
i2c->msg_num = 0;
if (ret)
i2c->msg_idx = ret;
//msg_num個(gè)msg都處理完則喚醒等待隊(duì)列
wake_up(&i2c->wait);
}
//應(yīng)答禁能
static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
{
unsigned long tmp;

tmp = readl(i2c->regs + S3C2410_IICCON);
writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
}
//應(yīng)答使能
static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
{
unsigned long tmp;

tmp = readl(i2c->regs + S3C2410_IICCON);
writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
}

/* irq enable/disable functions */
//中斷禁止
static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
{
unsigned long tmp;

tmp = readl(i2c->regs + S3C2410_IICCON);
writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
}
//中斷使能
static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
{
unsigned long tmp;

tmp = readl(i2c->regs + S3C2410_IICCON);
writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
}

/* s3c24xx_i2c_message_start
*
* put the start of a message onto the bus
*/
//寫入從器件地址，并發(fā)送起始信號(hào)
static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
struct i2c_msg *msg)
{
unsigned int addr = (msg->addr & 0x7f) << 1;//最低位為讀寫標(biāo)志
unsigned long stat;
unsigned long iiccon;

stat = 0;
stat |= S3C2410_IICSTAT_TXRXEN;//數(shù)據(jù)收發(fā)使能

if (msg->flags & I2C_M_RD) {
stat |= S3C2410_IICSTAT_MASTER_RX;
addr |= 1;//主機(jī)讀
} else
stat |= S3C2410_IICSTAT_MASTER_TX;//主機(jī)寫

if (msg->flags & I2C_M_REV_DIR_ADDR)
addr ^= 1;

/* todo - check for wether ack wanted or not */
s3c24xx_i2c_enable_ack(i2c);

iiccon = readl(i2c->regs + S3C2410_IICCON);
writel(stat, i2c->regs + S3C2410_IICSTAT);

dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DSn", stat, addr);
writeb(addr, i2c->regs + S3C2410_IICDS);

/* delay here to ensure the data byte has gotten onto the bus
* before the transaction is started */

ndelay(i2c->tx_setup);//延時(shí)等待SCL被釋放

dev_dbg(i2c->dev, "iiccon, %08lxn", iiccon);
writel(iiccon, i2c->regs + S3C2410_IICCON);

stat |= S3C2410_IICSTAT_START;
writel(stat, i2c->regs + S3C2410_IICSTAT);//發(fā)送起始信號(hào)
}

static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
{
unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);

dev_dbg(i2c->dev, "STOPn");

/* stop the transfer */
iicstat &= ~S3C2410_IICSTAT_START;
writel(iicstat, i2c->regs + S3C2410_IICSTAT);

i2c->state = STATE_STOP;
//數(shù)據(jù)發(fā)送結(jié)束，喚醒等待隊(duì)列
s3c24xx_i2c_master_complete(i2c, ret);
s3c24xx_i2c_disable_irq(i2c);
}

/* helper functions to determine the current state in the set of
* messages we are sending */

/* is_lastmsg()
*
* returns TRUE if the current message is the last in the set
*/
//msg_idx為當(dāng)前msg在msg_num個(gè)發(fā)送msg中的偏移，
static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
{
return i2c->msg_idx >= (i2c->msg_num - 1);
}

/* is_msglast
*
* returns TRUE if we this is the last byte in the current message
*/
//msg_ptr為在msg中的len個(gè)數(shù)據(jù)中的偏移
static inline int is_msglast(struct s3c24xx_i2c *i2c)
{
return i2c->msg_ptr == i2c->msg->len-1;
}

/* is_msgend
*
* returns TRUE if we reached the end of the current message
*/
//當(dāng)前msg中的數(shù)據(jù)處理完
static inline int is_msgend(struct s3c24xx_i2c *i2c)
{
return i2c->msg_ptr >= i2c->msg->len;
}

/* i2s_s3c_irq_nextbyte
*
* process an interrupt and work out what to do
*/

static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
{
unsigned long tmp;
unsigned char byte;
int ret = 0;

switch (i2c->state) {

case STATE_IDLE:
dev_err(i2c->dev, "%s: called in STATE_IDLEn", __func__);
goto out;
break;

case STATE_STOP:
dev_err(i2c->dev, "%s: called in STATE_STOPn", __func__);
s3c24xx_i2c_disable_irq(i2c);
goto out_ack;//如果當(dāng)前為停止?fàn)顟B(tài)則清除中斷掛起條件

case STATE_START://開始狀態(tài)在開始數(shù)據(jù)傳輸函數(shù)s3c24xx_i2c_doxfer中設(shè)置
/* last thing we did was send a start condition on the
* bus, or started a new i2c message
*/

if (iicstat & S3C2410_IICSTAT_LASTBIT &&
!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
/* ack was not received... */
//沒有收到應(yīng)答信號(hào)則停止數(shù)據(jù)傳輸
dev_dbg(i2c->dev, "ack was not receivedn");
s3c24xx_i2c_stop(i2c, -ENXIO);
goto out_ack;
}
//其實(shí)信號(hào)成功發(fā)送后決定接下來(lái)要做的事情
if (i2c->msg->flags & I2C_M_RD)
i2c->state = STATE_READ;
else
i2c->state = STATE_WRITE;

/* terminate the transfer if there is nothing to do
* as this is used by the i2c probe to find devices. */
//如果當(dāng)前msg是隊(duì)列中的最后一個(gè)而且沒有要發(fā)送的數(shù)據(jù)則停止
if (is_lastmsg(i2c) && i2c->msg->len == 0) {
s3c24xx_i2c_stop(i2c, 0);
goto out_ack;
}
//當(dāng)前中斷是起始信號(hào)成功發(fā)送，下一次中斷則是進(jìn)行數(shù)據(jù)接收，
//為接收數(shù)據(jù)準(zhǔn)備可用的緩存
if (i2c->state == STATE_READ)
goto prepare_read;

/* fall through to the write state, as we will need to
* send a byte as well */

case STATE_WRITE:
/* we are writing data to the device... check for the
* end of the message, and if so, work out what to do
*/

if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
if (iicstat & S3C2410_IICSTAT_LASTBIT) {
dev_dbg(i2c->dev, "WRITE: No Ackn");

s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
goto out_ack;
}
}

retry_write:

if (!is_msgend(i2c)) {
byte = i2c->msg->buf[i2c->msg_ptr++];
//i2c->msg_ptr++表明它總是指向第一個(gè)未被發(fā)送的數(shù)據(jù)
writeb(byte, i2c->regs + S3C2410_IICDS);
//如果當(dāng)前msg緩存中的數(shù)據(jù)沒有全部發(fā)送則繼續(xù)發(fā)送
/* delay after writing the byte to allow the
* data setup time on the bus, as writing the
* data to the register causes the first bit
* to appear on SDA, and SCL will change as
* soon as the interrupt is acknowledged */