1腳：通常連接到目標(biāo)板的vdd，用來檢測目標(biāo)系統(tǒng)是否供電;檢測原理上圖中有簡單的說明。
2腳：原版的JLink這個(gè)引腳沒有使用，不提供Vsupply輸出，而很多改造版的JLink通過跳線選擇從該引腳輸出3.3V的電壓給外邊，我的就是這樣的。
可以到網(wǎng)上找JLink的原理圖看看。
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0517b/Cjaeccji.html
JTAG interface signals
The following table describes the signals on the JTAG interfaces:
Table 1. JTAG signals
SignalI/ODescription
DBGACK-This pin is connected in the RVI run control unit, but is not supported in the current release of the software. It is reserved for compatibility with other equipment to be used as a debug acknowledge signal from the target system. It is recommended that this signal is pulled LOW on the target.
DBGRQ-This pin is connected in the RVI run control unit, but is not supported in the current release of the software. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. The RVI software maintains this signal as LOW.
When applicable,RVI uses the scan chain 2 of the processor to put the processor in debug state. It is recommended that this signal is pulled LOW on the target.
GND-Ground.
nSRSTInput/outputActive Low output from RVI to the target system reset, with a 4.7kΩ pull-up resistor for de-asserted state. This is also an input to RVI so that a reset initiated on the target can be reported to the debugger.
This pin must be pulled HIGH on the target to avoid unintentional resets when there is no connection.
nTRSTOutputActive Low output from RVI to the Reset signal on the target JTAG port, driven to the VTref voltage for de-asserted state. This pin must be pulled HIGH on the target to avoid unintentional resets when there is no connection.
RTCKInputReturn Test Clock signal from the target JTAG port to RVI. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. RVI provides Adaptive Clock Timing, that waits for TCK changes to be echoed correctly before making more changes. Targets that do not have to process TCK can ground this pin.
RTCK is not supported in Serial Wire Debug (SWD) mode.
TCKOutputTest Clock signal from RVI to the target JTAG port. It is recommended that this pin is pulled LOW on the target.
TDIOutputTest Data In signal from RVI to the target JTAG port. It is recommended that this pin is pulled HIGH on the target.
TDOInputTest Data Out from the target JTAG port to RVI. It is recommended that this pin is pulled HIGH on the target.
TMSOutputTest Mode signal from RVI to the target JTAG port. This pin must be pulled HIGH on the target so that the effect of any spurious TCKs when there is no connection is benign.
VsupplyInputThis pin is not connected in the RVI unit. It is reserved for compatibility with other equipment to be used as a power feed from the target system.
VTrefInputThis is the target reference voltage. It indicates that the target has power, and It must be at least 0.628V. VTref is normally fed from Vdd on the target hardware and might have a series resistor (though this is not recommended). There is a 10kΩ pull-down resistor on VTref in RVI.
ARM系統(tǒng)的JTAG接口的設(shè)計(jì)不當(dāng)往往使硬件系統(tǒng)無法調(diào)試，所以在設(shè)計(jì)ARM系統(tǒng)前要先熟悉ARM系統(tǒng)的JTAG接口的定義和常見問題。
1.ARM系統(tǒng)的JTAG接口是如何定義的? 每個(gè)PIN又是如何連接的?
下圖是JTAG接口的信號(hào)排列示意：
接口是一個(gè)20腳的IDC插座。下表給出了具體的信號(hào)說明：
表 1 JTAG引腳說明
序號(hào)信號(hào)名方向說 明
1VrefInput接口電平參考電壓，通?？芍苯咏与娫?
2VsupplyInput電源
3nTRSTOutput(可選項(xiàng)) JTAG復(fù)位。在目標(biāo)端應(yīng)加適當(dāng)?shù)纳侠娮枰苑乐拐`觸發(fā)。
4GND--接地
5TDIOutputTest Data In from Dragon-ICE to target.
6GND--接地
7TMSOutputTest Mode Select
8GND--接地
9TCKOutputTest Clock output from Dragon-ICE to the target
10GND--接地
11RTCKInput(可選項(xiàng)) Return Test Clock。由目標(biāo)端反饋給Dragon-ICE的時(shí)鐘信號(hào)，用來同步TCK信號(hào)的產(chǎn)生。不使用時(shí)可以直接接地。
12GND--接地
13TDOInputTest Data Out from target to Dragon-ICE.
14GND--接地
15nSRSTInput/Output(可選項(xiàng)) System Reset，與目標(biāo)板上的系統(tǒng)復(fù)位信號(hào)相連?？梢灾苯訉?duì)目標(biāo)系統(tǒng)復(fù)位，同時(shí)可以檢測目標(biāo)系統(tǒng)的復(fù)位情況。為了防止誤觸發(fā)，應(yīng)在目標(biāo)端加上適當(dāng)?shù)纳侠娮琛?
16GND--接地
17NC
保留
18GND--接地
19NC--保留
20GND--接地
2.目標(biāo)系統(tǒng)如何設(shè)計(jì)?
目標(biāo)板使用與Dragon-ICE一樣的20腳針座，信號(hào)排列見表1。RTCK和 nTRST這兩個(gè)信號(hào)根據(jù)目標(biāo)ASIC有否提供對(duì)應(yīng)的引腳來選用。nSRST則根據(jù)目標(biāo)系統(tǒng)的設(shè)計(jì)考慮來選擇使用。下面是一個(gè)典型的連接關(guān)系圖：
復(fù)位電路中可以根據(jù)不同的需要包含上電復(fù)位、手動(dòng)復(fù)位等等功能。如果用戶希望系統(tǒng)復(fù)位信號(hào)nSRST能同時(shí)觸發(fā)JTAG口的復(fù)位信號(hào)nTRST，則可以使用一些簡單的組合邏輯電路來達(dá)到要求。后面給出了一種電路方案的效果圖。
圖 3 一個(gè)復(fù)位電路結(jié)構(gòu)的例子
在目標(biāo)系統(tǒng)的PCB設(shè)計(jì)中，最好把JTAG接口放置得離目標(biāo)ASIC近一些，如果這兩者之間的連線過長，會(huì)影響JTAG口的通信速率。
另外電源的連線也需要加以額外考慮，因?yàn)镈ragon-ICE要從目標(biāo)板上吸取超過100mA的大電流。最好能有專門的敷銅層來供電，假如只能使用連線供電的話，最小線寬不應(yīng)小于10mil (0.254mm)。
3. 14腳JTAG如何與20JTAG連接?
Dragon-ICE使用工業(yè)標(biāo)準(zhǔn)的20腳JTAG插頭，但是有些老的系統(tǒng)采用一種14腳的插座
。這兩類接口的信號(hào)排列如下：
這兩類接口之間的信號(hào)電氣特性都是一樣的，因此可以把對(duì)應(yīng)的信號(hào)直接連起來進(jìn)
行轉(zhuǎn)接。Dragon-ICE配備這種轉(zhuǎn)接卡，隨機(jī)配備。
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