外媒：蘋(píng)果三星是制造3D芯片的關(guān)鍵

元器件交易網(wǎng)訊 11月12日消息，據(jù)外媒EETimes報(bào)道，蘋(píng)果與三星都在3D集成電路技術(shù)上發(fā)力。掌握該項(xiàng)技術(shù)將決定誰(shuí)將贏得未來(lái)消費(fèi)電子終端的霸主地位，以下為全文摘譯：

半導(dǎo)體產(chǎn)業(yè)僵局將被3D芯片堆疊技術(shù)打破，該技術(shù)將創(chuàng)造新一代高性能低能耗的系統(tǒng)。

這可能被Globalfoundries用來(lái)壓低競(jìng)爭(zhēng)對(duì)手臺(tái)積電代工的2.5D芯片價(jià)格—如果它制造得出來(lái)的話(huà)。也可能被三星用來(lái)蠶食蘋(píng)果的智能手機(jī)和平板市場(chǎng)。還有可能被英偉達(dá)用來(lái)從AMD手中搶占GPU市場(chǎng)份額，并且在精神上擊潰對(duì)方。

FPGA供應(yīng)商會(huì)描述今年二月國(guó)際固態(tài)電路會(huì)議上將兩個(gè)65nm串行器安在FPGA旁的產(chǎn)品，同樣蜂窩基站中ADC和DAC也可以安裝在FPGA旁。因此，這些成本相對(duì)較高，小批量產(chǎn)品的應(yīng)用正在慢慢擴(kuò)大。

像AMD和Nvidia這樣的顯卡芯片廠商很希望在他們的GPU旁的硅中層介質(zhì)中安裝3D內(nèi)存，這樣產(chǎn)品就能有更高的性能和更低的能耗。但仍沒(méi)有足夠的理由花費(fèi)10倍的額外費(fèi)用去制造它。

潛在客戶(hù)稱(chēng)3D存儲(chǔ)器公司還沒(méi)有準(zhǔn)備好提供高容量產(chǎn)品，也許要到明年才可以。他們還預(yù)計(jì)推出可支持的JEDECHBM接口圖形處理器的版本。但同時(shí)，價(jià)格仍舊是個(gè)問(wèn)題。

三星已經(jīng)有了所有的業(yè)務(wù)——DRAM，閃存，處理器和工廠，現(xiàn)已批量銷(xiāo)售4G內(nèi)存堆棧一段時(shí)間了，因此它具有一定的3D IC生產(chǎn)能力。

上周的ARM開(kāi)發(fā)者大會(huì)上，三星向與會(huì)者演示了3D內(nèi)存的樣品以及使用JedecWide IO接口的獵戶(hù)座處理器。它與傳統(tǒng)的獨(dú)立SoC及存儲(chǔ)器的智能手機(jī)相比能耗更低。但三星對(duì)其何時(shí)產(chǎn)品化不予置評(píng)。

“真” 3D堆棧在使用硅晶穿孔技術(shù)連接邏輯和內(nèi)存的使用者如智能手機(jī)的SoC上仍舊存在一些問(wèn)題 。比如沒(méi)有人知道如何去冷卻邏輯、如何使用EDA工具和技能展示TSV依舊是不成熟的。

當(dāng)使用3D集成電路制造智能手機(jī)合算時(shí)，三星的工程師都會(huì)有一個(gè)好想法。鑒于三星在移動(dòng)終端領(lǐng)域的銷(xiāo)量已經(jīng)領(lǐng)先于蘋(píng)果，發(fā)展這項(xiàng)新的充滿(mǎn)挑戰(zhàn)的技術(shù)將會(huì)是三星帶來(lái)的壓力消失的時(shí)候。

同時(shí)，觀戰(zhàn)者中的資深工程師指出的一個(gè)點(diǎn)讓每個(gè)人都感到驚訝。他拆解了蘋(píng)果iPhone5S中的A7處理器，處理器采用非常非常簡(jiǎn)單的六層結(jié)構(gòu)—其中兩層為信號(hào)層及地面信號(hào)層，他說(shuō)。存儲(chǔ)器本質(zhì)上是在簡(jiǎn)單的電路板的另一側(cè)。

他的拆解表明，蘋(píng)果已經(jīng)發(fā)現(xiàn)了一個(gè)3D半導(dǎo)體的低成本路徑。把大部分的智能放在SoC上，并使用一個(gè)簡(jiǎn)單的PC板作為“窮人版的3D半導(dǎo)體。”

也許下一代iPhone會(huì)將柔性電路或玻璃或有機(jī)插板插進(jìn)SoC和內(nèi)存之間。這是一個(gè)能讓無(wú)晶圓廠公司與晶圓廠企業(yè)巨頭如三星垂直競(jìng)爭(zhēng)的創(chuàng)舉。

所以大家非常關(guān)心幾件事：蘋(píng)果和三星將會(huì)在移動(dòng)終端領(lǐng)域做出什么動(dòng)作？還有臺(tái)積電與Globalfoundries及美光與SK海力士2.5D芯片的定價(jià)是多少？

誰(shuí)會(huì)先掌握3D芯片技術(shù)呢？

以下為原文：

SANJOSE, Calif. – The semiconductor industry is in a standoff over the next bigthing -- 3D chip stacks. Someone needs to blink before the technology will beviable for creating the next generation of high-performance, low-power systems.

Itmight be Globalfoundries undercutting rival TSMC on foundry prices for a 2.5Dprocess -- if it can deliver it. It might be Samsung trying to widen its edgeon Apple in smartphone and tablets. Or perhaps Nvidia will take a big hit onmargins (maybe even a loss) to grab a big chunk of GPU marketshare andmindshare from rival Advanced Micro Devices.

Thatwas the picture fromapanel discussionwherea member of the audience made a shocking disclosure the Apple A7 SoC in theiPhone 5s is "a poor man's 3D IC."

Xilinxtalked about how it is already shipping 2.5D stacks where die are laidside-by-side on a silicon interposer. So far it has discussed products usingmultiple FPGAs or an FPGA and serdes on a chip.

TheFPGA vendor will describe at theInternational Solid StateCircuits ConferenceinFebruary a product that puts two 65nm serdes next to an FPGA. It is also saidto be working on devices with an ADC and DAC next to an FPGA for use incellular base stations. So the applications for these relatively high-cost,low-volume products are slowly expanding.

Butso far the Xilinx products are consuming less than 200 wafers a month,according to estimates. So what's the path to high volumes of tens or hundredsof thousands of wafers per month? In a word, torturous.

Nextpages: Logic vs. memory fabs and Apple vs. Samsung.

TSMCclaims it's a one-stop shop for 2.5D stacks, and Globalfoundries is at somestage of bringing up its own service. Having one neck to choke for a complextechnology like 2.5D chips is great, but the foundries are charging a 10xpremium. Yikes!

Graphicschip vendors such as AMD and Nvidia would love to put a nice big 3D memorystack on a silicon interposer next to their honking GPUs. The resultingproducts would have significantly higher performance and lower power, but notenough to justify the 10x manufacturing premium the foundries are charging.

Sothe industry is at a chicken-and-egg stand still for high volume 2.5D products.

Micronhopes its Hybrid Memory Cube could be the break out product. But it's not clearits high-end customers are the right vehicle. Fujitsu said it will show aprototype board at next week's supercomputer conference using (it is believed)as many as eight of the HMC stacks.[!--empirenews.page--]

Sothe technology is real and has users, but not high-volume ones -- yet. SK Hynixwill show its own version of a memory stack that like Micron's has four toeight DRAM die delivering something on the order of 160 Mbytes/second, so thereis competition.

Potentialcustomers say neither 3D memory company is ready to supply high volumes yet.Perhaps they will next year. They are also expected to roll versions thatsupport the Jedec HBM interface for graphics processors. The question, again,comes down to price.

Atthe panel session, Abe Yee, a packaging expert at Nvidia, had some suggestionsfor the likes of Globalfoundries, Micron, SK Hynix, and TSMC.

"We'veinvested $2 billion in [the chip stacking] market already and haven't got itback, but we continue to invest -- and our suppliers need to think the sameway," Yee said.

"Idon't think Moore's Law is going to last another 20 years, and even if it doeswe will still need to get memory closer to processors," Yee added."So this market is going to happen if you like it or not, and suppliers haveto think about how they will invest in it," he said.

Ofcourse it's always easier to tell the other guy to invest the next billion.Meanwhile, the other billion dollar question is, what will Samsung do?"

TheKorean giant has all the pieces -- DRAM, flash, processors, and fabs. It hasbeen selling as merchant products for some time 4 Gbyte memory stacks, so ithas some 3D capabilities.

AtARMTech Conlastweek, Samsung even teased attendees with a demo of a 3D stack of memory and itsExynos application processor using a Jedec Wide IO interface. It deliveredsignificantly lower power than a traditional separate smartphone SoC andmemory. But Samsung would not comment on if or when it would become a product.

Thereare a few problems with the "true" 3D stacks using through siliconvias to connect logic and memory for uses like smartphone SoCs. No one knowshow to cool the logic, for instance, and the EDA tools and skills to lay out theTSVs are said to be immature.

Inany case, Samsung's engineers likely have a good idea when it is economical tomake a 3D IC for smartphones. Given it is already pulling ahead of Apple inmobile device volumes, the pressure may be off for the moment to jump to a newand risky technology.

Meanwhile,a veteran engineer in the audience at the panel surprised everyone when hechimed in with a data point. He had done a teardown of the Apple A7 processorin the iPhone 5S. It uses a very, very simple six layer board -- twolayers each for signal, ground and signal, he said. The memory is essentiallyon the other side of the simple board.

Hisanalysis suggests Apple has discovered a low cost path to 3D ICs. Put most ofthe smarts in the SoC and use a simple pc board as "a poor man's 3DIC."

Perhapsthe next iPhone will use an even simpler layer between its SoC and memory chipsuch as a flex circuit or a glass or organic interposer. It's a great way for afabless company to compete with vertically integrated giant like Samsung.

Soeveryone is watching a few things very closely. What will Apple and Samsung doin mobile. And what will TSMC vs. Globalfoundries and Micron vs. SK Hynix do in2.5D pricing.

Whodo you think will blink first?